Ettus Knowledge Base - User contributions [en]

B200/B210/B200mini/B205mini/B206mini

2025-11-12T23:20:19Z

DylanCaswell: /* Schematics */

== Device Overview ==
The USRP Bus Series provides a fully integrated, single board, Universal Software Radio Peripheral platform with continuous frequency coverage from 70 MHz – 6 GHz. Designed for low-cost experimentation, it combines a fully integrated direct conversion transceiver providing up to 56MHz of real-time bandwidth, an open and reprogrammable Spartan6 FPGA, and fast and convenient bus-powered SuperSpeed USB 3.0 connectivity.

== Key Features==
=== B200===
{|
|style="vertical-align:top"|
* Xilinx Spartan 6 XC6SLX75 FPGA
* Analog Devices AD9364 RFIC direct-conversion transceiver
* Frequency range: 70 MHz - 6 GHz
* Up to 56 MHz of instantaneous bandwidth
* Full duplex, SISO (1 Tx & 1 Rx)
* Fast and convenient bus-powered USB 3.0 connectivity
* Optional Board Mounted GPSDO
|[[File:Product b200.png|250px|center]]
|}

=== B210===
{|
|style="vertical-align:top"|
* Xilinx Spartan 6 XC6SLX150 FPGA
* Analog Devices AD9361 RFIC direct-conversion transceiver
* Frequency range: 70 MHz - 6 GHz
* Up to 56 MHz of instantaneous bandwidth (61.44MS/s quadrature)
* Full duplex, MIMO (2 Tx & 2 Rx)
* Fast and convenient bus-powered USB 3.0 connectivity
* Optional Board Mounted GPSDO
|[[File:Product b210.png|250px|center]]
|}

=== B200mini===
{|
|style="vertical-align:top"|
* Xilinx Spartan-6 XC6SLX75 FPGA
* Analog Devices AD9364 RFIC direct-conversion transceiver
* Frequency range: 70 MHz - 6 GHz
* Up to 56 MHz of instantaneous bandwidth
* Full duplex, SISO (1 Tx & 1 Rx)
* Fast and convenient bus-powered USB 3.0 connectivity
|[[File:Product b200 mini.png|250px|center]]
|}

=== B200mini-i===
{|
|style="vertical-align:top"|
* Industrial-grade Xilinx Spartan-6 XC6SLX75 FPGA
* Analog Devices AD9364 RFIC direct-conversion transceiver
* Frequency range: 70 MHz - 6 GHz
* Up to 56 MHz of instantaneous bandwidth
* Full duplex, SISO (1 Tx & 1 Rx)
* Fast and convenient bus-powered USB 3.0 connectivity
|[[File:Product b200 mini i.png|250px|center]]
|}

=== B205mini-i===
{|
|style="vertical-align:top"|
* Industrial-grade Xilinx Spartan-6 XC6SLX150 FPGA
* Analog Devices AD9364 RFIC direct-conversion transceiver
* Frequency range: 70 MHz - 6 GHz
* Up to 56 MHz of instantaneous bandwidth
* Full duplex, SISO (1 Tx & 1 Rx)
* Fast and convenient bus-powered USB 3.0 connectivity
|[[File:Product b200 mini i.png|250px|center]]
|}

=== B206mini-i===
{|
|style="vertical-align:top"|
* Industrial-grade Xilinx Spartan-6 XC6SLX150 FPGA
* Analog Devices AD9364 RFIC direct-conversion transceiver
* Frequency range: 70 MHz - 6 GHz
* Up to 56 MHz of instantaneous bandwidth
* Full duplex, SISO (1 Tx & 1 Rx)
* Fast and convenient bus-powered USB 3.0 connectivity
|[[File:Product b206 mini i.png|250px|center]]
|}

==Frontend Specifications==
===Tuning===

The RF frontend has individually tunable receive and transmit chains. On the B200/200mini/205mini/206mini, there is one transmit and one receive RF frontend. On the B210, both transmit and receive can be used in a MIMO configuration. For the MIMO case on the B210 only, both receive frontends share the RX LO, and both transmit frontends share the TX LO. Each LO is independently tunable between 50 MHz and 6 GHz and can be used with 1 or 2 channels; all channels using the same LO must use the same sampling parameters, including the sample rate and RF center frequency.

===Gains===
All frontends have individual analog gain controls. The receive frontends have 76 dB of available gain; and the transmit frontends have 89.8 dB of available gain. Gain settings are application specific, but it is recommended that users consider using at least half of the available gain to get reasonable dynamic range.

===Bandwidths===
The analog frontend has a seamlessly adjustable bandwidth of 200 kHz to 56 MHz.

Generally, when requesting any possible master clock rate, UHD will automatically configure the analog filters to avoid any aliasing (RX) or out-of-band emissions whilst letting through the cleanest possible signal.

If you, however, happen to have a very strong interferer within half the master clock rate of your RX LO frequency, you might want to reduce this analog bandwidth. You can do so by calling uhd::usrp::multi_usrp::set_rx_bandwidth(bw).

The property to control the analog RX bandwidth is bandwidth/value.

UHD will not allow you to set bandwidths larger than your current master clock rate.

==RF Specifications==
The USRP B200/210/200mini/205mini/206mini are derived from the Analog devices AD936x integrated transceiver chip. The overall RF performance of the device is largely governed by the transceiver chip itself.

===RF Performance===
* [https://www.ni.com/docs/en-US/bundle/usrp-b206mini-i-specs/ B206mini RF specifications]
* [https://www.ettus.com/wp-content/uploads/2019/01/USRP_B200mini_Data_Sheet-1.pdf B200mini/205mini RF specifications]
* [https://www.ettus.com/wp-content/uploads/2019/01/b200-b210_spec_sheet.pdf B200/210 RF specifications]
* SSB/LO Suppression: It is based on the AD9364 performance. Refer AD9364 [https://www.analog.com/media/en/technical-documentation/data-sheets/AD9364.pdf Datasheet] and [https://www.analog.com/media/cn/technical-documentation/user-guides/ad9364_reference_manual_ug-673.pdf Reference Manual] for more information.
* Tx Phase Noise: It is recommended to operate the USRP device on the following step size based on the following frequency ranges to get an optimal Phase Noise performance:
** 70MHz to 3GHz: 20MHz step size
** 3GHz to 6GHz: 40MHz step size

===Input/Output Impedance===
All RF Ports are matched to 50 Ohm with -10dB or better return loss generally. Detailed test is pending.

===Input Power Levels===
* The maximum input power for the B200/210/200mini/205mini/206mini is -15 dBm.

===RF Performance Data===
====B200mini / B205mini / B206mini====
* [[Media:B20xmini RF Performance Data.pdf]]

====B200 / B210====
* [[Media:B200 RF Performance.pdf]]

==Hardware Specifications==
* Ettus Research recommends to always use the latest stable version of UHD

=== B200===
* Current Hardware Revision: 6
* Minimum version of UHD required: 3.8.4
* B200 Rev 5 (AD9364-based board) requires minimum UHD 3.8.4

=== B210===
* Current Hardware Revision: 5
* Minimum version of UHD required: 3.6.0

=== B200mini===
* Current Hardware Revision: 2
* Minimum version of UHD required: 3.9.0

=== B200mini-i===
* Current Hardware Revision: 2
* Minimum version of UHD required: 3.9.0

=== B205mini-i===
* Current Hardware Revision: 1
* Minimum version of UHD required: 3.9.2

=== B206mini-i===
* Current Hardware Revision: 1
* Minimum version of UHD required: 4.9.0

==Physical Specifications==
===Dimensions===
* B206mini-i
** 8.4 x 5.1 x 0.8 cm (Board-only)
** 8.5 x 5.5 x 1.8 cm (Enclosed)
* B200mini/B205mini 5.0 x 8.4 cm
* B200/B210 9.7 x 15.5 x 1.5 cm

===Weight===
* B206mini
** Enclosed 108 g
** Board-only 25 g
* B200mini 24.0 g
* B200/B210 350 g

===Drawings===
====B206mini-i====
* [[Media:cu usrp b206mini-i cca.pdf| B206mini Board only]]
* [[Media:cu usrp b206mini-i.pdf| B206mini Enclosure]]

====B200mini====
* [[Media:B200mini_drawing.png| Board only]]
* [[Media:cu usrp-b200mini.pdf| B20xmini Enclosure]]

====B200====
* [[Media:cu ettus b200 cca.pdf| Board only]]

====B210====
* [[Media:cu ettus b210 cca.pdf| Board only]]

====B200/B210 Enclosure====
* [[Media:cu ettus-b2xx-full-enclosure.pdf|Enclosure]]

===CAD/STP Models===
====B206mini-i====
* [[Media:cu usrp b206mini-i.stp.tar.gz| B206mini with Enclosure]]
* [[Media:cu usrp b206mini-i enc.stp.tar.gz| Enclosure only]]
* [[Media:cu usrp b206mini-i cca.stp.tar.gz| Board only ]]

====B200mini====
* [[Media:B200mini.stp.tar.gz| B200mini with Enclosure]]
* [[Media:B200mini enclosure-only.stp.tar.gz| Enclosure only]]
* [[Media:cu ettus b200mini cca.stp.tar.gz| Board only ]]

====B20xmini-i====
* [[Media:b20xmini-i._thermal_insert.stp.tar.gz| B20xmini-i Thermal Insert]]

====B200====
* [[Media:cu ettus b200 cca.stp.tar.gz| Board only]]

====B210====
* [[Media:cu ettus b210 cca.stp.gz| Board only]]

====B200/B210 Enclosure====
* [[Media:cu ettus-b200-b210-case.zip|Enclosure]]

==Environmental Specifications==
===Operating Temperature Range===
* B200 / B210: 25 °C
* B200mini - Board Only: 0 - 40 °C
* B200mini - With Enclosure: -20 - 60°C
* B200mini-i / B205mini-i / B206mini - Board Only: 0 - 45 °C
* B200mini-i / B205mini-i / B206mini - With I-Grade Enclosure: -40 - 75°C

===Operating Humidity Range===
* 10% to 90% non-condensing

==Schematics==

===B200mini/B200mini-i/B205mini-i===
[http://files.ettus.com/schematics/b200mini/b200mini.pdf B200mini/B200mini-i/B205mini-i Schematics]

===B200/B210===
[http://files.ettus.com/schematics/b200/b210.pdf B200/B210 Schematics]

==Key Component Datasheets==
{| class="wikitable" style="width:80%"
!Part Number
!Description
!Schematic ID (Page)

|-
|[https://www.minicircuits.com/pdfs/TCM1-63AX+.pdf Mini-Circuits TCM1-63AX+]
|Transformer
|T1 (1,3); T2 (1,3)
|-

|-
|[http://www.analog.com/en/products/rf-microwave/integrated-transceivers-transmitters-receivers/wideband-transceivers-ic/ad9364.html#product-overview Analog Devices AD9364]
|RF Transceiver
|U1 (2)
|-
|[http://www.analog.com/en/products/rf-microwave/integrated-transceivers-transmitters-receivers/wideband-transceivers-ic/ad9361.html#product-overview Analog Devices AD9361]
|RF Transceiver
|U2 (2,8)
|-

|[https://www.analog.com/en/lp/001/integrated-rf-agile-transceiver-design-resources.html AD9361/AD9364 Product Page]
|RF Transceiver
| -
|-
|[http://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html Xilinx Spartan-6 Product Page]
|FPGA
|rowspan="2"|U1 (2,3,4,6); PG1 (6); U18B, U18C (7); U18D (8); U18E, U18F (9); U18G, U18H (10)
|-
|[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf XC6SLX75 / XC6SLX150]
|FPGA
|-
|[http://www.analog.com/media/en/technical-documentation/data-sheets/ADF4001.pdf ADF4001]
|Frequency Synthesizer
|U101 (1)
|-

|[http://www.cypress.com/file/140296/download CYUSB3014]
|rowspan="2"|FX3: SuperSpeed USB Controller
|rowspan="2"|U3 (5,6); U13 (5)
|-

|[http://www.cypress.com/applications/ez-usb-fx3-superspeed-usb-30-peripheral-controller-collateral-guide EZ-USB FX3™ Product Page]
|-

|[https://d1ehax0mqsd4rz.cloudfront.net/-/media/SkyWorks/Documents/Products/301-400/SKY13317-373LF_200914L.pdf?rev=9aae5568774a4ec69e6e3b6b335f4fc4 SKY13317]
|Antenna Switch
|U801, U810 (8)
|-
|[https://cdn.ttm.com/repository/products/wireless-xinger/balun-transformers/BD3150L50100AHF/BD3150L50100AHF.pdf BD3150L50100A00]
|Balun
|U802, U808, U809, U815 (8)
|-
|[https://www.minicircuits.com/pdfs/PGA-102+.pdf PGA−102+]
|Amplifier
|U804, U817 (8)
|-

|[https://support.epson.biz/td/api/doc_check.php?dl=brief_TG2520SMN&lang=en VCTCXO]
|VCTCXO (B200mini only)
| -
|-

|[https://support.epson.biz/td/api/doc_check.php?dl=brief_TG-5006CE&lang=en 525L20DA40M0000]
|VCTCXO (B200/B210 only)
| X100 (1)
|-

|[http://www.jackson-labs.com/index.php/products/lc_xo Jackson Labs LC_XO] [https://www.viavisolutions.com/en-us/literature/low-cost-desktop-gpsdo-module-kit-data-sheets-en.pdf Spec Sheet] [https://comms.viavisolutions.com/Request-PNT-Manuals-vs12228 Manual]
|Optional GPSDO (B200/B210 only)
|U100 (1)
|-
|}

==Enclosures==

* SMA connectors should be torqued to 4 inch-pounds

===B206mini-i===
* [https://www.ettus.com/all-products/usrp-b206mini-i-enclosure/ B206mini I-Grade Enclosure]

===B200mini===
* [https://www.ettus.com/all-products/usrp-b200mini-enclosure/ B200mini C-Grade Enclosure]
* [https://www.ettus.com/all-products/usrp-b200mini-i-enclosure/ B200mini I-Grade Enclosure]

===B205mini===
* [https://www.ettus.com/all-products/usrp-b205mini-i-enclosure/ B205mini I-Grade Enclosure]

===B200/B210===
* [https://www.ettus.com/product/details/USRP-B200-Enclosure USRP B200/B210 Enclosure]
** Full Steel Enclosure
** Compatible with green USRP B200 and B210 devices (revision 6 or later)
** Front and rear K-Slots for anti-theft protection

==FPGA==
* Utilization statistics are subject to change between UHD releases. This information is current as of UHD 3.9.4.
===B200===
<pre>
Device utilization summary:
---------------------------

Selected Device : 6slx75fgg484-3

Slice Logic Utilization:
Number of Slice Registers: 15781 out of 93296 16%
Number of Slice LUTs: 19987 out of 46648 42%
Number used as Logic: 15983 out of 46648 34%
Number used as Memory: 4004 out of 11072 36%
Number used as RAM: 972
Number used as SRL: 3032

Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 24062
Number with an unused Flip Flop: 8281 out of 24062 34%
Number with an unused LUT: 4075 out of 24062 16%
Number of fully used LUT-FF pairs: 11706 out of 24062 48%
Number of unique control sets: 434

IO Utilization:
Number of IOs: 172
Number of bonded IOBs: 155 out of 280 55%
IOB Flip Flops/Latches: 124

Specific Feature Utilization:
Number of Block RAM/FIFO: 144 out of 172 83%
Number using Block RAM only: 144
Number of BUFG/BUFGCTRLs: 4 out of 16 25%
Number of DSP48A1s: 76 out of 132 57%
</pre>

===B210===
<pre>
Device utilization summary:
---------------------------

Selected Device : 6slx150fgg484-3

Slice Logic Utilization:
Number of Slice Registers: 29310 out of 184304 15%
Number of Slice LUTs: 36486 out of 92152 39%
Number used as Logic: 29279 out of 92152 31%
Number used as Memory: 7207 out of 21680 33%
Number used as RAM: 1752
Number used as SRL: 5455

Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 43635
Number with an unused Flip Flop: 14325 out of 43635 32%
Number with an unused LUT: 7149 out of 43635 16%
Number of fully used LUT-FF pairs: 22161 out of 43635 50%
Number of unique control sets: 723

IO Utilization:
Number of IOs: 180
Number of bonded IOBs: 163 out of 338 48%
IOB Flip Flops/Latches: 148

Specific Feature Utilization:
Number of Block RAM/FIFO: 186 out of 268 69%
Number using Block RAM only: 186
Number of BUFG/BUFGCTRLs: 4 out of 16 25%
Number of DSP48A1s: 152 out of 180 84%
</pre>

===B200mini===
<pre>
Device utilization summary:
---------------------------

Selected Device : 6slx75csg484-3

Slice Logic Utilization:
Number of Slice Registers: 15949 out of 93296 17%
Number of Slice LUTs: 19963 out of 46648 42%
Number used as Logic: 16140 out of 46648 34%
Number used as Memory: 3823 out of 11072 34%
Number used as RAM: 972
Number used as SRL: 2851

Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 23859
Number with an unused Flip Flop: 7910 out of 23859 33%
Number with an unused LUT: 3896 out of 23859 16%
Number of fully used LUT-FF pairs: 12053 out of 23859 50%
Number of unique control sets: 429

IO Utilization:
Number of IOs: 123
Number of bonded IOBs: 114 out of 328 34%
IOB Flip Flops/Latches: 147

Specific Feature Utilization:
Number of Block RAM/FIFO: 110 out of 172 63%
Number using Block RAM only: 110
Number of BUFG/BUFGCTRLs: 6 out of 16 37%
Number of DSP48A1s: 76 out of 132 57%
Number of PLL_ADVs: 1 out of 6 16%
</pre>

===B205mini/B206mini===
<pre>
Device utilization summary:
---------------------------

Selected Device : 6slx150csg484-3

Slice Logic Utilization:
Number of Slice Registers: 15949 out of 184304 8%
Number of Slice LUTs: 19963 out of 92152 21%
Number used as Logic: 16140 out of 92152 17%
Number used as Memory: 3823 out of 21680 17%
Number used as RAM: 972
Number used as SRL: 2851

Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 23859
Number with an unused Flip Flop: 7910 out of 23859 33%
Number with an unused LUT: 3896 out of 23859 16%
Number of fully used LUT-FF pairs: 12053 out of 23859 50%
Number of unique control sets: 429

IO Utilization:
Number of IOs: 123
Number of bonded IOBs: 114 out of 338 33%
IOB Flip Flops/Latches: 147

Specific Feature Utilization:
Number of Block RAM/FIFO: 110 out of 268 41%
Number using Block RAM only: 110
Number of BUFG/BUFGCTRLs: 6 out of 16 37%
Number of DSP48A1s: 76 out of 180 42%
Number of PLL_ADVs: 1 out of 6 16%
</pre>

==Interfaces and Connectivity==
B200/B210/B200mini/B206mini - USB 3.0

===GPIO===
====Power on state====
The hardware power on state and UHD initial state for the front-panel GPIOs is high-Z. For the B2xx, B2xxmini there are no external pull-ups/pull-downs for the GPIO pins, but the FPGAs do have them and they are configured as follows: B2xx: pull-up, B2xxmini: pull-up.

====Output Current====
The GPIOs are configured as LVCMOS33 outputs with pull-ups on the B2xx. The strength for LVCMOS and LVTTL on Spartan 6 is 12 mA if not otherwise specified.

===Timing Reference Input===
====B200mini/B200mini-i/B205mini-i/B206mini-i====
* 1-PPS or 10 MHz input

=====1-PPS=====
* Maximum: -5V / +5V
* Minimum: 0V / +2.5V

=====10 MHz=====
* Maximum: 0V / +5V
* Minimum: 0V / +1.8V
'''OR'''
* +10dBm ~ +27dBm

====B200/B210====
=====1-PPS=====
* Maximum: 5V
=====10 MHz=====
* Maximum: 15dBm (3.5Vpp into 50 ohms)

==Certifications==
===RoHS===
As of December 1st, 2010 all Ettus Research products are RoHS compliant unless otherwise noted. More information can be found at [http://ettus.com/legal/rohs-information http://ettus.com/legal/rohs-information]

===China RoHS===
'''Management Methods for Controlling Pollution Caused by Electronic Information Products Regulation'''

'''Chinese Customers'''

National Instruments is in compliance with the Chinese policy on the Restriction of Hazardous Substances (RoHS) used in Electronic Information Products. For more information about the National Instruments China RoHS compliance, visit [http://www.ni.com/environment/rohs_china ni.com/environment/rohs_china].

===Certifications for European Union===
In order to ensure compliance with EU certifications for radio equipment, a ferrite bead (included in kits with NI part number 785825-01 and 785826-01) should be affixed onto the GPIO cable, if in use. This is achieved by opening the snap-on ferrite bead and enclosing it around the GPIO cable(s).

In addition to the part numbers listed above, these ferrite beads can be sourced through Fair-Rite using part number 0443164251.

==Certificate of Volatility==

Found on the [https://www.ni.com/en/support/documentation/product-certifications.html NI Product Certifications lookup tool]:
* [https://www.ni.com/pdf/manuals/377354a.pdf B200/B210 Letter of Volatility]
* [https://www.ni.com/pdf/manuals/377354a.pdf B200mini/205mini Letter of Volatility]
* [https://www.ni.com/docs/en-US/bundle/usrp-b206mini-i-lov/resource/usrp-b206mini-i-lov.pdf B206mini Letter of Volatility]

==Downloads==

[http://files.ettus.com/manual/md_fpga.html FPGA Resources]

[http://files.ettus.com/binaries/uhd_stable/ UHD Stable Binaries]

[https://github.com/EttusResearch/uhd UHD Source Code on Github]

==FAQ==
This is a list of frequently asked questions on the USRP [https://www.ettus.com/product/details/UB200-KIT B200]/[https://www.ettus.com/product/details/UB210-KIT B210]/[https://www.ettus.com/product/details/USRP-B200mini B200mini]. If you have questions that are not answered in this document, please contact us - [mailto:info@ettus.com info@ettus.com].

'''Will the USRP [https://www.ettus.com/product/details/UB200-KIT B200]/[https://www.ettus.com/product/details/UB210-KIT B210] work with USB 2.0?'''

Yes, both the USRP B200 and USRP B210 will fall back to the USB 2.0 standard if a USB 3.0 port is not available. There are several things to consider. First, the USB 2.0 data rates are slower. Depending on the USB controller, operating system, and other factors, you may achieve a sample rate up to 8 MS/s with USB 2.0. Also, you may not be able to bus-power the USRP B200/B210 in USB 2.0 mode.

'''What samples rates should I expect with USB 3.0? USB 2.0?'''

The performance and throughput of USB 3.0 can vary between host controllers. Ettus Research recommends using the Intel Series 7, 8, and 9 USB controllers. In Linux, the command <code>lspci</code> will show the USB controller on the system.

'''When can I power the USRP B200/B210/B200mini off USB?'''

The experience will vary across various controllers. Generally speaking, bus-power is ideal for SISO operation. If you are using both channels of a USRP B210 we recommend an external power supply. We [https://www.ettus.com/all-products/powersupply/ sell an external power supply that works with a variety of USRPs].

MIMO operation with the USRP B210 is not recommended when using the USRP B210 on bus-power. It is also not recommended to run the B210 on bus-power if a GPS-disciplined oscillator is installed.

'''How much power does the USRP consume?'''

The table below shows power consumption (Watts) of a USRP B210 run with a 6V power supply. Figures on a 5V supply (USB power), or with a USRP B200 will be moderately lower. The sample rates shown are aggregate sample rates on the USB 3.0 interface.

{| class="wikitable"
!
!5 Msps
!15.36 Msps
!30.72 Msps
!56 Msps
!61.44 Msps
|-
|1 RX
|1.92
|2.112
|2.184
|2.508
|
|-
|2 RX
|2.148
|2.436
|2.508
|2.64
|
|-
|1 TX
|2.184
|2.34
|2.352
|2.22
|
|-
|2 TX
|2.76
|2.88
|2.904
|2.64
|
|-
|Full Duplex (1x1)
|2.508
|2.736
|2.796
|3.168
|
|-
|2x2 MIMO
|3.252
|3.588
|3.672
|4.11
|4.092
|-
|}

'''Can I build a multi-unit system with the USRP B200/B210?'''

It is possible to synchronize multiple USRP B200/B210 devices using the 10 MHz/1 PPS inputs and an external distribution system like to the OctoClock-G. However, [http://www.ettus.com/kb/detail/usrp-b200-and-b210-usb-30-streaming-rate-benchmarks USB 3.0/2.0 performance] varies dramatically when multiple devices are streaming through the same controller. Generally, we recommend using the USRP N200/N210 if you need to build a high-channel count system.

'''Can I access the source code for the USRP B200/B210?'''

Yes. The USRP B200/B210 is supported by the USRP Hardware DriverTM software. You can find the driver and FPGA source code for the USRP B200/B210, and all other USRP models, in the UHD git repository:

http://files.ettus.com/manual/page_build_guide.html

'''What operating systems does the USRP B200/B210 work on?'''

The USRP B200/B210 is supported on [http://files.ettus.com/manual/page_install.html Linux, OSX (MacOSX / macOS) and Windows].

'''Does the USRP B200/B210 work with GNU Radio?'''

Yes. The USRP B200/B210 work with our GNU Radio plugin - gr-uhd.

'''Does the USRP B200/B210 work with MATLAB and Simulink?'''

Yes. You need to install the [http://www.mathworks.com/hardware-support/usrp.html Communications System Toolbox Support Package for USRP Radio].

'''Does the USRP B200/B210 work with OpenBTS?'''

Yes. This is a third-party application and you can find instructions here: [http://wush.net/trac/rangepublic/wiki/BuildInstallRun OpenBTS - Build, Install, Run.]

For support, please sign up and contact the [https://lists.sourceforge.net/lists/listinfo/openbts-discuss OpenBTS mailing list].

'''What tools do I need to program the FPGA?'''

The USRP [https://www.ettus.com/product/details/UB200-KIT B200] and USRP [https://www.ettus.com/product/details/UB210-KIT B210] include a Spartan 6 XC6SLX75 and XC6S150, respectively. The USRP B200 can be programmed with the free version of Xilinx tools, while the larger FPGA on the USRP B210 requires a licensed seat.

'''Can I use a GPSDO with the USRP B200/B210?'''

Ettus Research offers a [https://www.ettus.com/product/details/GPSDO-MINI Board-Mounted GPS-Disciplined OCXO] and a [https://www.ettus.com/product/details/GPSDO-TCXO-MODULE Board-Mounted GPS-Disciplined TCXO], which are compatible with the USRP B200/B210. These provide a high-accuracy XO, which can be disciplined to the global GPS standard. Please note: When the GPSDO OCXO model is integrated on the USRP B200/B210, the device should be powered with an external supply instead of USB bus power. The TCXO version can be USB bus powered.

[[Category:Hardware Resources]]

OBX

2025-09-29T21:16:18Z

DylanCaswell: /* Key Component Datasheets */

OBX

2025-09-29T21:15:34Z

DylanCaswell: /* OBX */

OBX

2025-09-29T21:14:13Z

DylanCaswell: /* Certificate of Volatility */

File:OBX-160 Letter of Volatility.pdf

2025-09-29T21:12:46Z

DylanCaswell:

OBX

2025-09-29T21:09:56Z

DylanCaswell: /* Shock and Vibration */

OBX

2025-09-23T19:30:29Z

DylanCaswell: /* Important Notes */

OBX

2025-09-23T19:29:18Z

DylanCaswell: /* Device Overview */

OBX Getting Started Guides

2025-09-23T19:28:12Z

DylanCaswell: /* Hardware Setup */

==Kit Contents==
* OBX-160 Daughterboard
* OBX-160 Installation Hardware (Washers, Nuts, Screws, Torx Key)
* 2x SMA F to SMPM F Cables
* SMPM Insertion/Extraction Tool
* Standoff Removal Wrench
* Safety, Environmental, and Regulatory Information (SERI)

{|
|[[File:OBX.jpg|250px|center]]
|[[File:OBX.X310.jpg|250px|center]]
|}

==USRP Compatibility==

===OBX-160===
* X Series only

==Hardware Setup==
[https://kb.ettus.com/USRP_X_Series_Quick_Start_(Daughterboard_Installation)#OBX-160_Instructions OBX-160 Installation Instructional Video]

==Proper Care and Handling==
All Ettus Research products are individually tested before shipment. The UBX is guaranteed to be functional at the time it is received by the customer. Improper use or handling of the UBX can easily cause the device to become non-functional. Listed below are some examples of actions which can prevent damage to the unit:

*Never allow metal objects to touch the circuit board while powered.
*Always properly terminate the transmit port with an antenna or 50Ω load.
*Always handle the board with proper anti-static methods.
*Never allow the board to directly or indirectly come into contact with any voltage spikes.
*Never allow any water, or condensing moisture, to come into contact with the boards.
*Always use caution with FPGA, firmware, or software modifications.
{|
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |Never apply more than -15 dBm of power into any RF input.
|-
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |Always use at least 30dB attenuation if operating in loopback configuration
|-
|}

==Technical Support and Community Knowledge Base==
Technical support for USRP hardware is available through email only. If the product arrived in a nonfunctional state or you require technical assistance, please contact [mailto:support@ettus.com support@ettus.com]. Please allow 24 to 48 hours for response by email, depending on holidays and weekends, although we are often able to reply more quickly than that.

We also recommend that you subscribe to the community mailing lists. The mailing lists have a responsive and knowledgeable community of hundreds of developers and technical users who are located around the world. When you join the community, you will be connected to this group of people who can help you learn about SDR and respond to your technical and specific questions. Often your question can be answered quickly on the mailing lists. Each mailing list also provides an archive of all past conversations and discussions going back many years. Your question or problem may have already been addressed before, and a relevant or helpful solution may already exist in the archive.

Discussions involving the USRP hardware and the UHD software itself are best addressed through the '''usrp-users''' mailing list at [http://usrp-users.ettus.com http://usrp-users.ettus.com].

Discussions involving the use of [http://gnuradio.org/ GNU Radio] with USRP hardware and UHD software are best addressed through the '''discuss-gnuradio''' mailing list at [https://lists.gnu.org/mailman/listinfo/discussgnuradio https://lists.gnu.org/mailman/listinfo/discussgnuradio].

Discussions involving the use of [http://openbts.org/ OpenBTS®] with USRP hardware and UHD software are best addressed through the '''openbts-discuss''' mailing list at [https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss].

The support page on our website is located at [https://www.ettus.com/support https://www.ettus.com/support]. The Knowledge Base is located at [https://kb.ettus.com https://kb.ettus.com].

==Legal Considerations==
Every country has laws governing the transmission and reception of radio signals. Users are solely responsible for insuring they use their USRP system in compliance with all applicable laws and regulations. Before attempting to transmit and/or receive on any frequency, we recommend that you determine what licenses may be required and what restrictions may apply.

==Sales and Ordering Support==
If you have any non-technical questions related to your order, then please contact us by email at [mailto:orders@ettus.com orders@ettus.com], or by phone at +14086106399 (Monday-Friday, 8 AM - 5 PM, Pacific Time). Please be sure to include your order number and the serial number of your USRP.

==Terms and Conditions of Sale==
Terms and conditions of sale can be accessed online at the following link: http://www.ettus.com/legal/terms-and-conditions-of-sale

[[Category:Getting Started Guides]]

Knowledge Base

2025-09-23T19:26:20Z

DylanCaswell: /* Hardware Resources */

Welcome to the Ettus Research Knowledge Base (KB). The KB is continuously being updated and expanded. If you have any suggestions, or do not find what you are looking for, then please [http://www.ettus.com/contact Contact Us].
__NOTOC__
<div class="row">
<div class="col-1-3">
== [[Getting Started Guides|<i class="fa fa-road"></i> Getting Started Guides]] ==

'''Motherboards'''
* [[B200/B210/B200mini/B205mini/B206mini Getting Started Guides|B200/B210/B200mini/B205mini/B206mini]]
* [[Ettus USRP E300 Embedded Family Getting Started Guides|E310/E312/E313]]
* [[E320 Getting Started Guide|E320]]
* [[N200/N210 Getting Started Guides|N200/N210]]
* [[USRP N300/N310/N320/N321 Getting Started Guide|N300/N310/N320/N321]]
* [[X300/X310 Getting Started Guides|X300/X310]]
* [[USRP-2974 Getting Started Guide|USRP-2974]]
* [[USRP X410/X440 Getting Started Guide|X410/X440]]

'''Daughterboards'''
* [[OBX Getting Started Guides|OBX]]
* [[BasicTX/BasicRX Getting Started Guides|BasicTX/BasicRX]]
* [[CBX Getting Started Guides|CBX]]
* [[LFTX/LFRX Getting Started Guides|LFTX/LFRX]]
* [[SBX Getting Started Guides|SBX]]
* [[TwinRX Getting Started Guides|TwinRX]]
* [[UBX Getting Started Guides|UBX]]
* [[WBX Getting Started Guides|WBX]]

'''Other'''
* [[Getting_Started_with_RFNoC_in_UHD_4.0|RFNoC Development (UHD 4.x)]]
* [[RFNoC_4_Migration_Guide|RFNoC Migration Guide (UHD 3.x to UHD 4.x)]]
* [[Getting_Started_with_RFNoC_Development|RFNoC Development (UHD 3.x)]]
* [[Live SDR Environment Getting Started Guides|Live SDR Environment]]
* [[OctoClock CDA-2990 Getting Started Guides|OctoClock CDA-2990]]
* [[Using Ethernet-Based Synchronization on the USRP™ N3xx Devices|White Rabbit]]
* [[Getting Started with DPDK and UHD|DPDK]]

</div>
<div class="col-1-3">

== [[Hardware Resources|<i class="fa fa-cogs"></i> Hardware Resources]] ==
'''Motherboards'''
* [[B200/B210/B200mini/B205mini/B206mini]]
* [[Ettus USRP E300 Embedded Family Hardware Resources|E310/E312/E313]]
* [[E320|E320]]
* [[N200/N210]]
* [[N300/N310]]
* [[N320/N321]]
* [[X300/X310]]
* [[USRP-2974]]
* [[X410]]
* [[X440]]

'''Daughterboards'''
* [[OBX]]
* [[BasicTX/BasicRX]]
* [[CBX]]
* [[LFTX/LFRX]]
* [[SBX]]
* [[TwinRX]]
* [[UBX]]
* [[WBX]]

'''Other'''
* [[OctoClock CDA-2990]]
* [[GPSDO]]
* [[Antennas]]

</div>
<div class="col-1-3">

== [[Software Resources|<i class="fa fa-desktop"></i> Software Resources]] ==
'''Ettus Products'''
* [[UHD]]
* [[UHD Python API]]
* [[RFNoC|RFNoC (UHD 4.x)]]
* [[RFNoC (UHD 3.0)|RFNoC (UHD 3.x)]]

'''Third Party'''
* [[GNU Radio]]
* [[LabVIEW]]
* [[Matlab/Simulink]]
* [[OpenBTS]]
* [[Eurecom OpenAirInterface (OAI)]]
* [[srsLTE/srsUE]]
* [[Gqrx]]
* [[Fosphor]]

'''Reference Architectures'''
* [[Multichannel RF Reference Architecture]]
* [[OAI Reference Architecture for 5G and 6G Research with USRP]]

</div>
</div>

<div class="row">
<div class="col-1-3">

== [[UHD and USRP User Manual|<i class="fa fa-flag"></i> UHD and USRP User Manual]] ==

'''Software'''
* [https://files.ettus.com/manual/ UHD Manual (master)]
* [https://files.ettus.com/manual_archive/ UHD Manual Archive (previous releases)]

'''Motherboards'''
* [https://files.ettus.com/manual/page_usrp_b200.html B200/B210/B200mini/B205mini/B206mini]
* [https://files.ettus.com/manual/page_usrp_x3x0.html X300/X310]
* [https://files.ettus.com/manual/page_usrp2.html N200/N210]
* [https://files.ettus.com/manual/page_usrp_n3xx.html N300/N310/N320/N321]
* [https://files.ettus.com/manual/page_usrp_e3xx.html E310/E312/E313/E320]
* [https://files.ettus.com/manual/page_usrp_x4xx.html X410/X440]

'''Daughterboards'''
* [https://files.ettus.com/manual/page_dboards.html#dboards_basictx BasicRX/LFRX]
* [https://files.ettus.com/manual/page_dboards.html#dboards_basicrx BasicTX/LFTX]
* [https://files.ettus.com/manual/page_dboards.html#dboards_cbx CBX]
* [https://files.ettus.com/manual/page_dboards.html#dboards_sbx SBX]
* [https://files.ettus.com/manual/page_dboards.html#dboards_wbx WBX]
* [https://files.ettus.com/manual/page_dboards.html#dboards_ubx UBX]
* [https://files.ettus.com/manual/page_dboards.html#dboards_twinrx TwinRX]

'''Other'''
* [https://files.ettus.com/manual/page_octoclock.html OctoClock]

</div>
<div class="col-1-3">

== [[Application Notes|<i class="fa fa-file-text-o"></i> Application Notes]] ==
Application Notes (AN) and technical articles written by engineers, for engineers. These articles offer experienced analysis, design ideas, reference designs, and tutorials—to make you productive and successful using USRP devices.
</div>
<div class="col-1-3">

== [[Additional Resources|<i class="fa fa-book"></i> Additional Resources]] ==
* [[Workshop_Tutorial|Workshop/Tutorial]]
* [[Suggested Reading|Suggested Reading]]
* [[Suggested Videos|Suggested Videos]]
* [[CGRAN]]
* [[SDR Events]]
* [[GNU Radio Conference]]
* [[NEWSDR]]
* [[FOSDEM]]
* [[Cyberspectrum]]
</div>
</div>

<div class="row">
<div class="col-1-3">

== [[Technical Support|<i class="fa fa-life-ring"></i> Technical Support]] ==
* [[Email|Email]]
* [[Mailing Lists|Mailing Lists]]
* [[Matrix|GNU Radio Matrix Chat Server]]
* [[SDR_Boston_Slack|SDR Boston Slack Chat Server]]
* [[StackExchange|StackExchange]]
* [[NI_SRM|NI Service Request Manager (SRM)]]

</div>
<div class="col-1-3">

== [[Faq|<i class="fa fa-info-circle"></i> FAQ]] ==
* [[Technical FAQ|Technical]]
* [[Licensing FAQ|Licensing]]

</div>
<div class="col-1-3">

== [[Legacy Products| <i class="fa fa-hourglass-end"></i> Legacy Products]] ==
'''Motherboards'''
* [[USRP1|USRP1]]
* [[USRP2|USRP2]]
* [[E100/E110|E100/E110]]
* [[B100]]

'''Daughterboards'''
* [[DBSRX2]]
* [[TVRX2]]
* [[XCVR2450]]

Knowledge Base

2025-09-23T19:25:51Z

DylanCaswell: /* Getting Started Guides */

Welcome to the Ettus Research Knowledge Base (KB). The KB is continuously being updated and expanded. If you have any suggestions, or do not find what you are looking for, then please [http://www.ettus.com/contact Contact Us].
__NOTOC__
<div class="row">
<div class="col-1-3">
== [[Getting Started Guides|<i class="fa fa-road"></i> Getting Started Guides]] ==

'''Motherboards'''
* [[B200/B210/B200mini/B205mini/B206mini Getting Started Guides|B200/B210/B200mini/B205mini/B206mini]]
* [[Ettus USRP E300 Embedded Family Getting Started Guides|E310/E312/E313]]
* [[E320 Getting Started Guide|E320]]
* [[N200/N210 Getting Started Guides|N200/N210]]
* [[USRP N300/N310/N320/N321 Getting Started Guide|N300/N310/N320/N321]]
* [[X300/X310 Getting Started Guides|X300/X310]]
* [[USRP-2974 Getting Started Guide|USRP-2974]]
* [[USRP X410/X440 Getting Started Guide|X410/X440]]

'''Daughterboards'''
* [[OBX Getting Started Guides|OBX]]
* [[BasicTX/BasicRX Getting Started Guides|BasicTX/BasicRX]]
* [[CBX Getting Started Guides|CBX]]
* [[LFTX/LFRX Getting Started Guides|LFTX/LFRX]]
* [[SBX Getting Started Guides|SBX]]
* [[TwinRX Getting Started Guides|TwinRX]]
* [[UBX Getting Started Guides|UBX]]
* [[WBX Getting Started Guides|WBX]]

'''Other'''
* [[Getting_Started_with_RFNoC_in_UHD_4.0|RFNoC Development (UHD 4.x)]]
* [[RFNoC_4_Migration_Guide|RFNoC Migration Guide (UHD 3.x to UHD 4.x)]]
* [[Getting_Started_with_RFNoC_Development|RFNoC Development (UHD 3.x)]]
* [[Live SDR Environment Getting Started Guides|Live SDR Environment]]
* [[OctoClock CDA-2990 Getting Started Guides|OctoClock CDA-2990]]
* [[Using Ethernet-Based Synchronization on the USRP™ N3xx Devices|White Rabbit]]
* [[Getting Started with DPDK and UHD|DPDK]]

</div>
<div class="col-1-3">

== [[Hardware Resources|<i class="fa fa-cogs"></i> Hardware Resources]] ==
'''Motherboards'''
* [[B200/B210/B200mini/B205mini/B206mini]]
* [[Ettus USRP E300 Embedded Family Hardware Resources|E310/E312/E313]]
* [[E320|E320]]
* [[N200/N210]]
* [[N300/N310]]
* [[N320/N321]]
* [[X300/X310]]
* [[USRP-2974]]
* [[X410]]
* [[X440]]

'''Daughterboards'''
* [[BasicTX/BasicRX]]
* [[CBX]]
* [[LFTX/LFRX]]
* [[SBX]]
* [[TwinRX]]
* [[UBX]]
* [[WBX]]

'''Other'''
* [[OctoClock CDA-2990]]
* [[GPSDO]]
* [[Antennas]]

</div>
<div class="col-1-3">

== [[Software Resources|<i class="fa fa-desktop"></i> Software Resources]] ==
'''Ettus Products'''
* [[UHD]]
* [[UHD Python API]]
* [[RFNoC|RFNoC (UHD 4.x)]]
* [[RFNoC (UHD 3.0)|RFNoC (UHD 3.x)]]

'''Third Party'''
* [[GNU Radio]]
* [[LabVIEW]]
* [[Matlab/Simulink]]
* [[OpenBTS]]
* [[Eurecom OpenAirInterface (OAI)]]
* [[srsLTE/srsUE]]
* [[Gqrx]]
* [[Fosphor]]

'''Reference Architectures'''
* [[Multichannel RF Reference Architecture]]
* [[OAI Reference Architecture for 5G and 6G Research with USRP]]

</div>
</div>

<div class="row">
<div class="col-1-3">

== [[UHD and USRP User Manual|<i class="fa fa-flag"></i> UHD and USRP User Manual]] ==

'''Software'''
* [https://files.ettus.com/manual/ UHD Manual (master)]
* [https://files.ettus.com/manual_archive/ UHD Manual Archive (previous releases)]

'''Motherboards'''
* [https://files.ettus.com/manual/page_usrp_b200.html B200/B210/B200mini/B205mini/B206mini]
* [https://files.ettus.com/manual/page_usrp_x3x0.html X300/X310]
* [https://files.ettus.com/manual/page_usrp2.html N200/N210]
* [https://files.ettus.com/manual/page_usrp_n3xx.html N300/N310/N320/N321]
* [https://files.ettus.com/manual/page_usrp_e3xx.html E310/E312/E313/E320]
* [https://files.ettus.com/manual/page_usrp_x4xx.html X410/X440]

'''Daughterboards'''
* [https://files.ettus.com/manual/page_dboards.html#dboards_basictx BasicRX/LFRX]
* [https://files.ettus.com/manual/page_dboards.html#dboards_basicrx BasicTX/LFTX]
* [https://files.ettus.com/manual/page_dboards.html#dboards_cbx CBX]
* [https://files.ettus.com/manual/page_dboards.html#dboards_sbx SBX]
* [https://files.ettus.com/manual/page_dboards.html#dboards_wbx WBX]
* [https://files.ettus.com/manual/page_dboards.html#dboards_ubx UBX]
* [https://files.ettus.com/manual/page_dboards.html#dboards_twinrx TwinRX]

'''Other'''
* [https://files.ettus.com/manual/page_octoclock.html OctoClock]

</div>
<div class="col-1-3">

== [[Application Notes|<i class="fa fa-file-text-o"></i> Application Notes]] ==
Application Notes (AN) and technical articles written by engineers, for engineers. These articles offer experienced analysis, design ideas, reference designs, and tutorials—to make you productive and successful using USRP devices.
</div>
<div class="col-1-3">

== [[Additional Resources|<i class="fa fa-book"></i> Additional Resources]] ==
* [[Workshop_Tutorial|Workshop/Tutorial]]
* [[Suggested Reading|Suggested Reading]]
* [[Suggested Videos|Suggested Videos]]
* [[CGRAN]]
* [[SDR Events]]
* [[GNU Radio Conference]]
* [[NEWSDR]]
* [[FOSDEM]]
* [[Cyberspectrum]]
</div>
</div>

<div class="row">
<div class="col-1-3">

== [[Technical Support|<i class="fa fa-life-ring"></i> Technical Support]] ==
* [[Email|Email]]
* [[Mailing Lists|Mailing Lists]]
* [[Matrix|GNU Radio Matrix Chat Server]]
* [[SDR_Boston_Slack|SDR Boston Slack Chat Server]]
* [[StackExchange|StackExchange]]
* [[NI_SRM|NI Service Request Manager (SRM)]]

</div>
<div class="col-1-3">

== [[Faq|<i class="fa fa-info-circle"></i> FAQ]] ==
* [[Technical FAQ|Technical]]
* [[Licensing FAQ|Licensing]]

</div>
<div class="col-1-3">

== [[Legacy Products| <i class="fa fa-hourglass-end"></i> Legacy Products]] ==
'''Motherboards'''
* [[USRP1|USRP1]]
* [[USRP2|USRP2]]
* [[E100/E110|E100/E110]]
* [[B100]]

'''Daughterboards'''
* [[DBSRX2]]
* [[TVRX2]]
* [[XCVR2450]]

OBX

2025-09-23T19:24:44Z

DylanCaswell:

USRP X Series Quick Start (Daughterboard Installation)

2025-09-23T18:55:39Z

DylanCaswell:

==Application Note Number==
'''AN-904'''

==Revision History==
{| class="wikitable"
!Date
!Author
!Details
|-
|style="text-align:center;"| 2016-05-01
|style="text-align:center;"| Neel Pandeya<br> Nate Temple
|style="text-align:center;"| Initial creation
|
|-
|style="text-align:center;"| 2020-Apr-27
|style="text-align:center;"| Jose Loera
|style="text-align:center;"| Added section "UBX Daughterboard Installation Video" and link. Link also provided [https://drive.google.com/file/d/1cMMxuV_KZVrc5r-NOwNLI9JoaGM8aUIu/view?usp=sharing here] as well
|-
|style="text-align:center;"| 2025-September
|style="text-align:center;"| Dylan Caswell<br> Patrick Alladio
|style="text-align:center;"| Added section "OBX-160 Daughterboard Installation Video" and link. Link also provided [https://files.ettus.com/app_notes/OBX_160_Installation.mp4]
|}

==Abstract==
This application note is a detailed step-by-step guide to install a daughterboard into the USRP X300/X310.

==OBX-160 Instructions==
Please refer to the following installation video for instructions on physically installing the OBX-160 into an X300/X310. The below content as it relates to software and X300/X310 usage still applies.

[https://files.ettus.com/app_notes/OBX_160_Installation.mp4 OBX-160 Installation Video]

==Overview==
This Quick Start is meant to show you how to put together your new X300/310. We will start at the point when you have yet to unpack the boxes and go all the way to being able to ping the device, performing a quick software probe to verify hardware components and finally running a simple FFT demo. This Quick Start does not cover the installation of software on the host computer. If you have not installed UHD/Gnuradio on your system, please reference the Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on [[Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on Linux|Linux]], [[Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on OS X|OS X]] and [[Building and Installing the USRP Open Source Toolchain (UHD and GNU Radio) on Windows|Windows]] Application Notes. You may also use the [[Live SDR Environment]] to perform the verification steps for your USRP. Detailed information on the [[Live SDR Environment]] is available at the [[Live SDR Environment Getting Started Guides]] page.

==Tools Required==
* Philips Screwdriver
* 5/16” wrench

==Pre-installed Software==
* UHD Latest
* GNU Radio

==Box Contents==
===USRP Box===
* 1 x USRP X300/X310
* 1 x SFP Adapter for 1 GigE
* 1 x Power Supply and US Cord
* 1 x USB 2.0 JTAG Debug Cable
* 1 x Gigabit Ethernet Cable
* 4 x SMA-Bulkhead Cables
* 16 x Daughterboard Screws
===Daughterboard Boxes===
* 2 x SBX Daughterboards
===Antenna Boxes===
* One or more Antennas

[[File:Caution.png|24px|left]] Notice This product is not approved or licensed for transmission over the air using an antenna. As a result, operating this product with an antenna
may violate local laws. Ensure that you are in compliance with all local laws before operating this product with an antenna.

[[File:Xseries quickstart figure 1.png|700px|center]]

[[File:Xseries quickstart figure 2.png|700px|center]]

==Proper Care and Handling==
All Ettus Research products are individually tested before shipment. The USRP™ is guaranteed to be functional at the time it is received by the customer. Improper use or handling of the USRP™ can easily cause the device to become non-functional. Ettus Research recommends you perform the installation with no power to the USRP and using ESD equipment. Listed below are some examples of actions which can prevent damage to the unit:

*Never allow metal objects to touch the circuit board while powered.
*Always properly terminate the transmit port with an antenna or 50Ω load.
*Always handle the board with proper anti-static methods.
*Never allow the board to directly or indirectly come into contact with any voltage spikes.
*Never allow any water, or condensing moisture, to come into contact with the boards.
*Always use caution with FPGA, firmware, or software modifications.
{|
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |Never apply more than -15 dBm of power into any RF input.
|-
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |Always use at least 30dB attenuation if operating in loopback configuration
|-
|}

==Installation Process==
===Step 1===
Unscrew the 2 screws on the top of the USRP and remove cover. (Lift up about 15 degrees and wiggle back as there
is a flange on the front part of the cover)

[[File:Xseries quickstart figure 3.png|700px|center]]

[[File:Xseries quickstart figure 4.png|700px|center]]

[[File:Xseries quickstart figure 5.png|700px|center]]

===Step 2===
Line up the 8 screw holes on the Daughterboard with the USRP Motherboard standoffs (they only go one way).

[[File:Xseries quickstart figure 6.png|700px|center]]

[[File:Xseries quickstart figure 7.png|700px|center]]

===Step 3===
After you have aligned the Daughterboard correctly you can press the Daughterboard on to the connectors below them (you will feel them snap into place).

[[File:Xseries quickstart figure 8.png|700px|center]]

[[File:Xseries quickstart figure 9.png|700px|center]]

===Step 4===
Put 8 of the screws provided in the daughterboard

[[File:Xseries quickstart figure 10.png|700px|center]]

===Step 5===
Repeat steps 2- 4 for the second Daughterboard

===Step 6===
It is recommended to connect the bulkhead cables one at a time to avoid confusion. The Daughterboards and front
panel of the X300/310 are clearly labeled as to which cable goes where.

[[File:Xseries quickstart figure 11.png|700px|center]]

[[File:Xseries quickstart figure 12.png|700px|center]]

[[File:Xseries quickstart figure 13.png|700px|center]]

[[File:Xseries quickstart figure 14.png|700px|center]]

[[File:Xseries quickstart figure 15.png|700px|center]]

[[File:Xseries quickstart figure 16.png|700px|center]]

===Step 7===
Repeat step 6 for the other bulkhead cables

[[File:Xseries quickstart figure 17.png|700px|center]]

[[File:Xseries quickstart figure 18.png|700px|center]]

===Step 8===
Install USRP cover with screws

[[File:Xseries quickstart figure 19.png|700px|center]]

===Step 9===
Connect the SFP 1 GigE adapter into USRP SFP port 0

[[File:Xseries quickstart figure 20.png|700px|center]]

[[File:Xseries quickstart figure 21.png|700px|center]]

===Step 10===
Connect the Gigabit Ethernet cable and power cord provided

[[File:Xseries quickstart figure 22.png|700px|center]]

===Step 11===
Attach any Antennas you may have purchased

[[File:Xseries quickstart figure 23.png|700px|center]]

===Step 12===
On the computer(host) you plan to use to connect to the USRP set the Ethernet adapter to have an IP address of 192.168.10.1 with a subnet mask of 255.255.255.0. Connect the other end of the Gigabit Ethernet cable to your computer.

[[File:Xseries quickstart figure 24.png|700px|center]]

===Step 13===
Power on the USRP (button on the front right of the USRP)

===Step 14===
Ping the device from host computer:

$ ping 192.168.10.2

[[File:Xseries quickstart figure 25.png|700px|center]]

===Step 15===
Assuming you have properly installed the UHD driver you can now run this command in a terminal/command window:

$ uhd_usrp_probe

This will tell you about the hardware inside of your USRP. The output will look like the following:

$ uhd_usrp_probe
linux; GNU C++ version 4.8.4; Boost_105400; UHD_003.010.git-202-g9e0861e1

-- X300 initialization sequence...
-- Determining maximum frame size... 1472 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...
-- Setup RF frontend clocking...
-- Radio 1x clock:200
-- Detecting internal GPSDO.... No GPSDO found
-- Initialize Radio0 control...
-- Performing register loopback test... pass
-- Initialize Radio1 control...
-- Performing register loopback test... pass
_____________________________________________________
/
| Device: X-Series Device
| _____________________________________________________
| /
| | Mboard: X300
| | revision: 7
| | revision_compat: 7
| | product: 30518
| | mac-addr0: ff:ff:ff:ff:ff:ff
| | mac-addr1: ff:ff:ff:ff:ff:ff
| | gateway: 255.255.255.255
| | ip-addr0: 255.255.255.255
| | subnet0: 255.255.255.255
| | ip-addr1: 255.255.255.255
| | subnet1: 255.255.255.255
| | ip-addr2: 255.255.255.255
| | subnet2: 255.255.255.255
| | ip-addr3: 255.255.255.255
| | subnet3: 255.255.255.255
| | serial: FFFFFFF
| | FW Version: 4.0
| | FPGA Version: 20.0
| |
| | Time sources: internal, external, gpsdo
| | Clock sources: internal, external, gpsdo
| | Sensors: ref_locked
| | _____________________________________________________
| | /
| | | RX DSP: 0
| | | Freq range: -100.000 to 100.000 MHz
| | _____________________________________________________
| | /
| | | RX DSP: 1
| | | Freq range: -100.000 to 100.000 MHz
| | _____________________________________________________
| | /
| | | RX Dboard: A
| | | ID: SBX (0x0054)
| | | Serial: FFFFFF
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 0
| | | | Name: SBXv3 RX
| | | | Antennas: TX/RX, RX2, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 400.000 to 4400.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 40000000.0 to 40000000.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: A
| | | | Name: ads62p48
| | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
| | _____________________________________________________
| | /
| | | RX Dboard: B
| | | ID: SBX (0x0054)
| | | Serial: FFFFFF
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 0
| | | | Name: SBXv3 RX
| | | | Antennas: TX/RX, RX2, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 400.000 to 4400.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 40000000.0 to 40000000.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: B
| | | | Name: ads62p48
| | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
| | _____________________________________________________
| | /
| | | TX DSP: 0
| | | Freq range: -100.000 to 100.000 MHz
| | _____________________________________________________
| | /
| | | TX DSP: 1
| | | Freq range: -100.000 to 100.000 MHz
| | _____________________________________________________
| | /
| | | TX Dboard: A
| | | ID: SBX (0x0055)
| | | Serial: FFFFFF
| | | _____________________________________________________
| | | /
| | | | TX Frontend: 0
| | | | Name: SBXv3 TX
| | | | Antennas: TX/RX, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 400.000 to 4400.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 40000000.0 to 40000000.0 step 0.0 Hz
| | | | Connection Type: QI
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: A
| | | | Name: ad9146
| | | | Gain Elements: None
| | _____________________________________________________
| | /
| | | TX Dboard: B
| | | ID: SBX (0x0055)
| | | Serial: FFFFFF
| | | _____________________________________________________
| | | /
| | | | TX Frontend: 0
| | | | Name: SBXv3 TX
| | | | Antennas: TX/RX, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 400.000 to 4400.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 40000000.0 to 40000000.0 step 0.0 Hz
| | | | Connection Type: QI
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: B
| | | | Name: ad9146
| | | | Gain Elements: None

==UBX daughterboard Installation Video==
The following link is a video of the steps to install the UBX daughterboard. The procedure is similar to what is outlined above.

*[https://drive.google.com/file/d/1cMMxuV_KZVrc5r-NOwNLI9JoaGM8aUIu/view?usp=sharing Video: UBX Installation into a USRP X-series device.]

==UHD FFT==
Try the UHD_FFT demo that comes with GNU Radio

1. Connect one antenna to RX2 on the left Daughterboard (Daughterboard A)

[[File:Xseries quickstart figure 26.png|700px|center]]

2.From the terminal/command window:

$ uhd_fft --ant RX2

[[File:Xseries quickstart figure 27.png|700px|center]]

[[File:Xseries quickstart figure 28.png|700px|center]]

==Success==
Congratulations! You have successfully setup and verified your new USRP X300/X310. A more detailed verification guide is at the [[Verifying the Operation of the USRP Using UHD and GNU Radio]] application note. For additional step-by-step guides to using your USRP X300/X310, see the [[Application Notes]] section of the [https://kb.ettus.com Ettus Research Knowledge Base].

OBX

2025-09-09T14:25:31Z

DylanCaswell: /* Drawings */

File:cu ettus OBX cca 2d.pdf

2025-09-09T14:24:56Z

DylanCaswell: OBX CCA 2d PDF

OBX CCA 2d PDF

File:cu ettus OBX cca.stp

2025-09-09T14:23:53Z

DylanCaswell: STP File for OBX

STP File for OBX

USRP X Series Quick Start (Daughterboard Installation)

2025-09-08T17:56:40Z

DylanCaswell: /* Antenna Boxes */

==Application Note Number==
'''AN-904'''

==Revision History==
{| class="wikitable"
!Date
!Author
!Details
|-
|style="text-align:center;"| 2016-05-01
|style="text-align:center;"| Neel Pandeya<br> Nate Temple
|style="text-align:center;"| Initial creation
|
|-
|style="text-align:center;"| 2020-Apr-27
|style="text-align:center;"| Jose Loera
|style="text-align:center;"| Added section "UBX Daughterboard Installation Video" and link. Link also provided [https://drive.google.com/file/d/1cMMxuV_KZVrc5r-NOwNLI9JoaGM8aUIu/view?usp=sharing here] as well
|}

==Abstract==
This application note is a detailed step-by-step guide to install a daughterboard into the USRP X300/X310.

==Overview==
This Quick Start is meant to show you how to put together your new X300/310. We will start at the point when you have yet to unpack the boxes and go all the way to being able to ping the device, performing a quick software probe to verify hardware components and finally running a simple FFT demo. This Quick Start does not cover the installation of software on the host computer. If you have not installed UHD/Gnuradio on your system, please reference the Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on [[Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on Linux|Linux]], [[Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on OS X|OS X]] and [[Building and Installing the USRP Open Source Toolchain (UHD and GNU Radio) on Windows|Windows]] Application Notes. You may also use the [[Live SDR Environment]] to perform the verification steps for your USRP. Detailed information on the [[Live SDR Environment]] is available at the [[Live SDR Environment Getting Started Guides]] page.

==Tools Required==
* Philips Screwdriver
* 5/16” wrench

==Pre-installed Software==
* UHD Latest
* GNU Radio

==Box Contents==
===USRP Box===
* 1 x USRP X300/X310
* 1 x SFP Adapter for 1 GigE
* 1 x Power Supply and US Cord
* 1 x USB 2.0 JTAG Debug Cable
* 1 x Gigabit Ethernet Cable
* 4 x SMA-Bulkhead Cables
* 16 x Daughterboard Screws
===Daughterboard Boxes===
* 2 x SBX Daughterboards
===Antenna Boxes===
* One or more Antennas

[[File:Caution.png|24px|left]] Notice This product is not approved or licensed for transmission over the air using an antenna. As a result, operating this product with an antenna
may violate local laws. Ensure that you are in compliance with all local laws before operating this product with an antenna.

[[File:Xseries quickstart figure 1.png|700px|center]]

[[File:Xseries quickstart figure 2.png|700px|center]]

==Proper Care and Handling==
All Ettus Research products are individually tested before shipment. The USRP™ is guaranteed to be functional at the time it is received by the customer. Improper use or handling of the USRP™ can easily cause the device to become non-functional. Ettus Research recommends you perform the installation with no power to the USRP and using ESD equipment. Listed below are some examples of actions which can prevent damage to the unit:

*Never allow metal objects to touch the circuit board while powered.
*Always properly terminate the transmit port with an antenna or 50Ω load.
*Always handle the board with proper anti-static methods.
*Never allow the board to directly or indirectly come into contact with any voltage spikes.
*Never allow any water, or condensing moisture, to come into contact with the boards.
*Always use caution with FPGA, firmware, or software modifications.
{|
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |Never apply more than -15 dBm of power into any RF input.
|-
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |Always use at least 30dB attenuation if operating in loopback configuration
|-
|}

==Installation Process==
===Step 1===
Unscrew the 2 screws on the top of the USRP and remove cover. (Lift up about 15 degrees and wiggle back as there
is a flange on the front part of the cover)

[[File:Xseries quickstart figure 3.png|700px|center]]

[[File:Xseries quickstart figure 4.png|700px|center]]

[[File:Xseries quickstart figure 5.png|700px|center]]

===Step 2===
Line up the 8 screw holes on the Daughterboard with the USRP Motherboard standoffs (they only go one way).

[[File:Xseries quickstart figure 6.png|700px|center]]

[[File:Xseries quickstart figure 7.png|700px|center]]

===Step 3===
After you have aligned the Daughterboard correctly you can press the Daughterboard on to the connectors below them (you will feel them snap into place).

[[File:Xseries quickstart figure 8.png|700px|center]]

[[File:Xseries quickstart figure 9.png|700px|center]]

===Step 4===
Put 8 of the screws provided in the daughterboard

[[File:Xseries quickstart figure 10.png|700px|center]]

===Step 5===
Repeat steps 2- 4 for the second Daughterboard

===Step 6===
It is recommended to connect the bulkhead cables one at a time to avoid confusion. The Daughterboards and front
panel of the X300/310 are clearly labeled as to which cable goes where.

[[File:Xseries quickstart figure 11.png|700px|center]]

[[File:Xseries quickstart figure 12.png|700px|center]]

[[File:Xseries quickstart figure 13.png|700px|center]]

[[File:Xseries quickstart figure 14.png|700px|center]]

[[File:Xseries quickstart figure 15.png|700px|center]]

[[File:Xseries quickstart figure 16.png|700px|center]]

===Step 7===
Repeat step 6 for the other bulkhead cables

[[File:Xseries quickstart figure 17.png|700px|center]]

[[File:Xseries quickstart figure 18.png|700px|center]]

===Step 8===
Install USRP cover with screws

[[File:Xseries quickstart figure 19.png|700px|center]]

===Step 9===
Connect the SFP 1 GigE adapter into USRP SFP port 0

[[File:Xseries quickstart figure 20.png|700px|center]]

[[File:Xseries quickstart figure 21.png|700px|center]]

===Step 10===
Connect the Gigabit Ethernet cable and power cord provided

[[File:Xseries quickstart figure 22.png|700px|center]]

===Step 11===
Attach any Antennas you may have purchased

[[File:Xseries quickstart figure 23.png|700px|center]]

===Step 12===
On the computer(host) you plan to use to connect to the USRP set the Ethernet adapter to have an IP address of 192.168.10.1 with a subnet mask of 255.255.255.0. Connect the other end of the Gigabit Ethernet cable to your computer.

[[File:Xseries quickstart figure 24.png|700px|center]]

===Step 13===
Power on the USRP (button on the front right of the USRP)

===Step 14===
Ping the device from host computer:

$ ping 192.168.10.2

[[File:Xseries quickstart figure 25.png|700px|center]]

===Step 15===
Assuming you have properly installed the UHD driver you can now run this command in a terminal/command window:

$ uhd_usrp_probe

This will tell you about the hardware inside of your USRP. The output will look like the following:

$ uhd_usrp_probe
linux; GNU C++ version 4.8.4; Boost_105400; UHD_003.010.git-202-g9e0861e1

-- X300 initialization sequence...
-- Determining maximum frame size... 1472 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...
-- Setup RF frontend clocking...
-- Radio 1x clock:200
-- Detecting internal GPSDO.... No GPSDO found
-- Initialize Radio0 control...
-- Performing register loopback test... pass
-- Initialize Radio1 control...
-- Performing register loopback test... pass
_____________________________________________________
/
| Device: X-Series Device
| _____________________________________________________
| /
| | Mboard: X300
| | revision: 7
| | revision_compat: 7
| | product: 30518
| | mac-addr0: ff:ff:ff:ff:ff:ff
| | mac-addr1: ff:ff:ff:ff:ff:ff
| | gateway: 255.255.255.255
| | ip-addr0: 255.255.255.255
| | subnet0: 255.255.255.255
| | ip-addr1: 255.255.255.255
| | subnet1: 255.255.255.255
| | ip-addr2: 255.255.255.255
| | subnet2: 255.255.255.255
| | ip-addr3: 255.255.255.255
| | subnet3: 255.255.255.255
| | serial: FFFFFFF
| | FW Version: 4.0
| | FPGA Version: 20.0
| |
| | Time sources: internal, external, gpsdo
| | Clock sources: internal, external, gpsdo
| | Sensors: ref_locked
| | _____________________________________________________
| | /
| | | RX DSP: 0
| | | Freq range: -100.000 to 100.000 MHz
| | _____________________________________________________
| | /
| | | RX DSP: 1
| | | Freq range: -100.000 to 100.000 MHz
| | _____________________________________________________
| | /
| | | RX Dboard: A
| | | ID: SBX (0x0054)
| | | Serial: FFFFFF
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 0
| | | | Name: SBXv3 RX
| | | | Antennas: TX/RX, RX2, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 400.000 to 4400.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 40000000.0 to 40000000.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: A
| | | | Name: ads62p48
| | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
| | _____________________________________________________
| | /
| | | RX Dboard: B
| | | ID: SBX (0x0054)
| | | Serial: FFFFFF
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 0
| | | | Name: SBXv3 RX
| | | | Antennas: TX/RX, RX2, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 400.000 to 4400.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 40000000.0 to 40000000.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: B
| | | | Name: ads62p48
| | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
| | _____________________________________________________
| | /
| | | TX DSP: 0
| | | Freq range: -100.000 to 100.000 MHz
| | _____________________________________________________
| | /
| | | TX DSP: 1
| | | Freq range: -100.000 to 100.000 MHz
| | _____________________________________________________
| | /
| | | TX Dboard: A
| | | ID: SBX (0x0055)
| | | Serial: FFFFFF
| | | _____________________________________________________
| | | /
| | | | TX Frontend: 0
| | | | Name: SBXv3 TX
| | | | Antennas: TX/RX, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 400.000 to 4400.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 40000000.0 to 40000000.0 step 0.0 Hz
| | | | Connection Type: QI
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: A
| | | | Name: ad9146
| | | | Gain Elements: None
| | _____________________________________________________
| | /
| | | TX Dboard: B
| | | ID: SBX (0x0055)
| | | Serial: FFFFFF
| | | _____________________________________________________
| | | /
| | | | TX Frontend: 0
| | | | Name: SBXv3 TX
| | | | Antennas: TX/RX, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 400.000 to 4400.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 40000000.0 to 40000000.0 step 0.0 Hz
| | | | Connection Type: QI
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: B
| | | | Name: ad9146
| | | | Gain Elements: None

==UBX daughterboard Installation Video==
The following link is a video of the steps to install the UBX daughterboard. The procedure is similar to what is outlined above.

*[https://drive.google.com/file/d/1cMMxuV_KZVrc5r-NOwNLI9JoaGM8aUIu/view?usp=sharing Video: UBX Installation into a USRP X-series device.]

==UHD FFT==
Try the UHD_FFT demo that comes with GNU Radio

1. Connect one antenna to RX2 on the left Daughterboard (Daughterboard A)

[[File:Xseries quickstart figure 26.png|700px|center]]

2.From the terminal/command window:

$ uhd_fft --ant RX2

[[File:Xseries quickstart figure 27.png|700px|center]]

[[File:Xseries quickstart figure 28.png|700px|center]]

==Success==
Congratulations! You have successfully setup and verified your new USRP X300/X310. A more detailed verification guide is at the [[Verifying the Operation of the USRP Using UHD and GNU Radio]] application note. For additional step-by-step guides to using your USRP X300/X310, see the [[Application Notes]] section of the [https://kb.ettus.com Ettus Research Knowledge Base].

USRP X Series Quick Start (Daughterboard Installation)

2025-09-08T17:54:51Z

DylanCaswell: /* Antenna Boxes */

==Application Note Number==
'''AN-904'''

==Revision History==
{| class="wikitable"
!Date
!Author
!Details
|-
|style="text-align:center;"| 2016-05-01
|style="text-align:center;"| Neel Pandeya<br> Nate Temple
|style="text-align:center;"| Initial creation
|
|-
|style="text-align:center;"| 2020-Apr-27
|style="text-align:center;"| Jose Loera
|style="text-align:center;"| Added section "UBX Daughterboard Installation Video" and link. Link also provided [https://drive.google.com/file/d/1cMMxuV_KZVrc5r-NOwNLI9JoaGM8aUIu/view?usp=sharing here] as well
|}

==Abstract==
This application note is a detailed step-by-step guide to install a daughterboard into the USRP X300/X310.

==Overview==
This Quick Start is meant to show you how to put together your new X300/310. We will start at the point when you have yet to unpack the boxes and go all the way to being able to ping the device, performing a quick software probe to verify hardware components and finally running a simple FFT demo. This Quick Start does not cover the installation of software on the host computer. If you have not installed UHD/Gnuradio on your system, please reference the Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on [[Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on Linux|Linux]], [[Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on OS X|OS X]] and [[Building and Installing the USRP Open Source Toolchain (UHD and GNU Radio) on Windows|Windows]] Application Notes. You may also use the [[Live SDR Environment]] to perform the verification steps for your USRP. Detailed information on the [[Live SDR Environment]] is available at the [[Live SDR Environment Getting Started Guides]] page.

==Tools Required==
* Philips Screwdriver
* 5/16” wrench

==Pre-installed Software==
* UHD Latest
* GNU Radio

==Box Contents==
===USRP Box===
* 1 x USRP X300/X310
* 1 x SFP Adapter for 1 GigE
* 1 x Power Supply and US Cord
* 1 x USB 2.0 JTAG Debug Cable
* 1 x Gigabit Ethernet Cable
* 4 x SMA-Bulkhead Cables
* 16 x Daughterboard Screws
===Daughterboard Boxes===
* 2 x SBX Daughterboards
===Antenna Boxes===
* One or more Antennas

Notice This product is not approved or licensed for transmission over the air using an antenna. As a result, operating this product with an antenna
may violate local laws. Ensure that you are in compliance with all local laws before operating this product with an antenna.

[[File:Xseries quickstart figure 1.png|700px|center]]

[[File:Xseries quickstart figure 2.png|700px|center]]

==Proper Care and Handling==
All Ettus Research products are individually tested before shipment. The USRP™ is guaranteed to be functional at the time it is received by the customer. Improper use or handling of the USRP™ can easily cause the device to become non-functional. Ettus Research recommends you perform the installation with no power to the USRP and using ESD equipment. Listed below are some examples of actions which can prevent damage to the unit:

*Never allow metal objects to touch the circuit board while powered.
*Always properly terminate the transmit port with an antenna or 50Ω load.
*Always handle the board with proper anti-static methods.
*Never allow the board to directly or indirectly come into contact with any voltage spikes.
*Never allow any water, or condensing moisture, to come into contact with the boards.
*Always use caution with FPGA, firmware, or software modifications.
{|
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |Never apply more than -15 dBm of power into any RF input.
|-
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |Always use at least 30dB attenuation if operating in loopback configuration
|-
|}

==Installation Process==
===Step 1===
Unscrew the 2 screws on the top of the USRP and remove cover. (Lift up about 15 degrees and wiggle back as there
is a flange on the front part of the cover)

[[File:Xseries quickstart figure 3.png|700px|center]]

[[File:Xseries quickstart figure 4.png|700px|center]]

[[File:Xseries quickstart figure 5.png|700px|center]]

===Step 2===
Line up the 8 screw holes on the Daughterboard with the USRP Motherboard standoffs (they only go one way).

[[File:Xseries quickstart figure 6.png|700px|center]]

[[File:Xseries quickstart figure 7.png|700px|center]]

===Step 3===
After you have aligned the Daughterboard correctly you can press the Daughterboard on to the connectors below them (you will feel them snap into place).

[[File:Xseries quickstart figure 8.png|700px|center]]

[[File:Xseries quickstart figure 9.png|700px|center]]

===Step 4===
Put 8 of the screws provided in the daughterboard

[[File:Xseries quickstart figure 10.png|700px|center]]

===Step 5===
Repeat steps 2- 4 for the second Daughterboard

===Step 6===
It is recommended to connect the bulkhead cables one at a time to avoid confusion. The Daughterboards and front
panel of the X300/310 are clearly labeled as to which cable goes where.

[[File:Xseries quickstart figure 11.png|700px|center]]

[[File:Xseries quickstart figure 12.png|700px|center]]

[[File:Xseries quickstart figure 13.png|700px|center]]

[[File:Xseries quickstart figure 14.png|700px|center]]

[[File:Xseries quickstart figure 15.png|700px|center]]

[[File:Xseries quickstart figure 16.png|700px|center]]

===Step 7===
Repeat step 6 for the other bulkhead cables

[[File:Xseries quickstart figure 17.png|700px|center]]

[[File:Xseries quickstart figure 18.png|700px|center]]

===Step 8===
Install USRP cover with screws

[[File:Xseries quickstart figure 19.png|700px|center]]

===Step 9===
Connect the SFP 1 GigE adapter into USRP SFP port 0

[[File:Xseries quickstart figure 20.png|700px|center]]

[[File:Xseries quickstart figure 21.png|700px|center]]

===Step 10===
Connect the Gigabit Ethernet cable and power cord provided

[[File:Xseries quickstart figure 22.png|700px|center]]

===Step 11===
Attach any Antennas you may have purchased

[[File:Xseries quickstart figure 23.png|700px|center]]

===Step 12===
On the computer(host) you plan to use to connect to the USRP set the Ethernet adapter to have an IP address of 192.168.10.1 with a subnet mask of 255.255.255.0. Connect the other end of the Gigabit Ethernet cable to your computer.

[[File:Xseries quickstart figure 24.png|700px|center]]

===Step 13===
Power on the USRP (button on the front right of the USRP)

===Step 14===
Ping the device from host computer:

$ ping 192.168.10.2

[[File:Xseries quickstart figure 25.png|700px|center]]

===Step 15===
Assuming you have properly installed the UHD driver you can now run this command in a terminal/command window:

$ uhd_usrp_probe

This will tell you about the hardware inside of your USRP. The output will look like the following:

$ uhd_usrp_probe
linux; GNU C++ version 4.8.4; Boost_105400; UHD_003.010.git-202-g9e0861e1

-- X300 initialization sequence...
-- Determining maximum frame size... 1472 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...
-- Setup RF frontend clocking...
-- Radio 1x clock:200
-- Detecting internal GPSDO.... No GPSDO found
-- Initialize Radio0 control...
-- Performing register loopback test... pass
-- Initialize Radio1 control...
-- Performing register loopback test... pass
_____________________________________________________
/
| Device: X-Series Device
| _____________________________________________________
| /
| | Mboard: X300
| | revision: 7
| | revision_compat: 7
| | product: 30518
| | mac-addr0: ff:ff:ff:ff:ff:ff
| | mac-addr1: ff:ff:ff:ff:ff:ff
| | gateway: 255.255.255.255
| | ip-addr0: 255.255.255.255
| | subnet0: 255.255.255.255
| | ip-addr1: 255.255.255.255
| | subnet1: 255.255.255.255
| | ip-addr2: 255.255.255.255
| | subnet2: 255.255.255.255
| | ip-addr3: 255.255.255.255
| | subnet3: 255.255.255.255
| | serial: FFFFFFF
| | FW Version: 4.0
| | FPGA Version: 20.0
| |
| | Time sources: internal, external, gpsdo
| | Clock sources: internal, external, gpsdo
| | Sensors: ref_locked
| | _____________________________________________________
| | /
| | | RX DSP: 0
| | | Freq range: -100.000 to 100.000 MHz
| | _____________________________________________________
| | /
| | | RX DSP: 1
| | | Freq range: -100.000 to 100.000 MHz
| | _____________________________________________________
| | /
| | | RX Dboard: A
| | | ID: SBX (0x0054)
| | | Serial: FFFFFF
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 0
| | | | Name: SBXv3 RX
| | | | Antennas: TX/RX, RX2, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 400.000 to 4400.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 40000000.0 to 40000000.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: A
| | | | Name: ads62p48
| | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
| | _____________________________________________________
| | /
| | | RX Dboard: B
| | | ID: SBX (0x0054)
| | | Serial: FFFFFF
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 0
| | | | Name: SBXv3 RX
| | | | Antennas: TX/RX, RX2, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 400.000 to 4400.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 40000000.0 to 40000000.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: B
| | | | Name: ads62p48
| | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
| | _____________________________________________________
| | /
| | | TX DSP: 0
| | | Freq range: -100.000 to 100.000 MHz
| | _____________________________________________________
| | /
| | | TX DSP: 1
| | | Freq range: -100.000 to 100.000 MHz
| | _____________________________________________________
| | /
| | | TX Dboard: A
| | | ID: SBX (0x0055)
| | | Serial: FFFFFF
| | | _____________________________________________________
| | | /
| | | | TX Frontend: 0
| | | | Name: SBXv3 TX
| | | | Antennas: TX/RX, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 400.000 to 4400.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 40000000.0 to 40000000.0 step 0.0 Hz
| | | | Connection Type: QI
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: A
| | | | Name: ad9146
| | | | Gain Elements: None
| | _____________________________________________________
| | /
| | | TX Dboard: B
| | | ID: SBX (0x0055)
| | | Serial: FFFFFF
| | | _____________________________________________________
| | | /
| | | | TX Frontend: 0
| | | | Name: SBXv3 TX
| | | | Antennas: TX/RX, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 400.000 to 4400.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 40000000.0 to 40000000.0 step 0.0 Hz
| | | | Connection Type: QI
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: B
| | | | Name: ad9146
| | | | Gain Elements: None

==UBX daughterboard Installation Video==
The following link is a video of the steps to install the UBX daughterboard. The procedure is similar to what is outlined above.

*[https://drive.google.com/file/d/1cMMxuV_KZVrc5r-NOwNLI9JoaGM8aUIu/view?usp=sharing Video: UBX Installation into a USRP X-series device.]

==UHD FFT==
Try the UHD_FFT demo that comes with GNU Radio

1. Connect one antenna to RX2 on the left Daughterboard (Daughterboard A)

[[File:Xseries quickstart figure 26.png|700px|center]]

2.From the terminal/command window:

$ uhd_fft --ant RX2

[[File:Xseries quickstart figure 27.png|700px|center]]

[[File:Xseries quickstart figure 28.png|700px|center]]

==Success==
Congratulations! You have successfully setup and verified your new USRP X300/X310. A more detailed verification guide is at the [[Verifying the Operation of the USRP Using UHD and GNU Radio]] application note. For additional step-by-step guides to using your USRP X300/X310, see the [[Application Notes]] section of the [https://kb.ettus.com Ettus Research Knowledge Base].

OBX Getting Started Guides

2025-09-04T15:11:59Z

DylanCaswell: /* Kit Contents */

==Kit Contents==
* OBX-160 Daughterboard
* OBX-160 Installation Hardware (Washers, Nuts, Screws, Torx Key)
* 2x SMA F to SMPM F Cables
* SMPM Insertion/Extraction Tool
* Standoff Removal Wrench
* Safety, Environmental, and Regulatory Information (SERI)

{|
|[[File:OBX.jpg|250px|center]]
|[[File:OBX.X310.jpg|250px|center]]
|}

==USRP Compatibility==

===OBX-160===
* X Series only

==Hardware Setup==
Installation instructions pending

==Proper Care and Handling==
All Ettus Research products are individually tested before shipment. The UBX is guaranteed to be functional at the time it is received by the customer. Improper use or handling of the UBX can easily cause the device to become non-functional. Listed below are some examples of actions which can prevent damage to the unit:

*Never allow metal objects to touch the circuit board while powered.
*Always properly terminate the transmit port with an antenna or 50Ω load.
*Always handle the board with proper anti-static methods.
*Never allow the board to directly or indirectly come into contact with any voltage spikes.
*Never allow any water, or condensing moisture, to come into contact with the boards.
*Always use caution with FPGA, firmware, or software modifications.
{|
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |Never apply more than -15 dBm of power into any RF input.
|-
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |Always use at least 30dB attenuation if operating in loopback configuration
|-
|}

==Technical Support and Community Knowledge Base==
Technical support for USRP hardware is available through email only. If the product arrived in a nonfunctional state or you require technical assistance, please contact [mailto:support@ettus.com support@ettus.com]. Please allow 24 to 48 hours for response by email, depending on holidays and weekends, although we are often able to reply more quickly than that.

We also recommend that you subscribe to the community mailing lists. The mailing lists have a responsive and knowledgeable community of hundreds of developers and technical users who are located around the world. When you join the community, you will be connected to this group of people who can help you learn about SDR and respond to your technical and specific questions. Often your question can be answered quickly on the mailing lists. Each mailing list also provides an archive of all past conversations and discussions going back many years. Your question or problem may have already been addressed before, and a relevant or helpful solution may already exist in the archive.

Discussions involving the USRP hardware and the UHD software itself are best addressed through the '''usrp-users''' mailing list at [http://usrp-users.ettus.com http://usrp-users.ettus.com].

Discussions involving the use of [http://gnuradio.org/ GNU Radio] with USRP hardware and UHD software are best addressed through the '''discuss-gnuradio''' mailing list at [https://lists.gnu.org/mailman/listinfo/discussgnuradio https://lists.gnu.org/mailman/listinfo/discussgnuradio].

Discussions involving the use of [http://openbts.org/ OpenBTS®] with USRP hardware and UHD software are best addressed through the '''openbts-discuss''' mailing list at [https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss].

The support page on our website is located at [https://www.ettus.com/support https://www.ettus.com/support]. The Knowledge Base is located at [https://kb.ettus.com https://kb.ettus.com].

==Legal Considerations==
Every country has laws governing the transmission and reception of radio signals. Users are solely responsible for insuring they use their USRP system in compliance with all applicable laws and regulations. Before attempting to transmit and/or receive on any frequency, we recommend that you determine what licenses may be required and what restrictions may apply.

==Sales and Ordering Support==
If you have any non-technical questions related to your order, then please contact us by email at [mailto:orders@ettus.com orders@ettus.com], or by phone at +14086106399 (Monday-Friday, 8 AM - 5 PM, Pacific Time). Please be sure to include your order number and the serial number of your USRP.

==Terms and Conditions of Sale==
Terms and conditions of sale can be accessed online at the following link: http://www.ettus.com/legal/terms-and-conditions-of-sale

[[Category:Getting Started Guides]]

OBX Getting Started Guides

2025-09-04T15:08:45Z

DylanCaswell: /* Kit Contents */

==Kit Contents==
* OBX Daughterboard
* OBX Installation Hardware (Washers, Nuts, Screws, Torx Key)
* 2x SMA F to SMPM F Cables
* SMPM Insertion/Extraction Tool
* Standoff Removal Wrench
* Safety, Environmental, and Regulatory Information (SERI)

{|
|[[File:OBX.jpg|250px|center]]
|[[File:OBX.X310.jpg|250px|center]]
|}

==USRP Compatibility==

===OBX-160===
* X Series only

==Hardware Setup==
Installation instructions pending

==Proper Care and Handling==
All Ettus Research products are individually tested before shipment. The UBX is guaranteed to be functional at the time it is received by the customer. Improper use or handling of the UBX can easily cause the device to become non-functional. Listed below are some examples of actions which can prevent damage to the unit:

*Never allow metal objects to touch the circuit board while powered.
*Always properly terminate the transmit port with an antenna or 50Ω load.
*Always handle the board with proper anti-static methods.
*Never allow the board to directly or indirectly come into contact with any voltage spikes.
*Never allow any water, or condensing moisture, to come into contact with the boards.
*Always use caution with FPGA, firmware, or software modifications.
{|
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |Never apply more than -15 dBm of power into any RF input.
|-
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |Always use at least 30dB attenuation if operating in loopback configuration
|-
|}

==Technical Support and Community Knowledge Base==
Technical support for USRP hardware is available through email only. If the product arrived in a nonfunctional state or you require technical assistance, please contact [mailto:support@ettus.com support@ettus.com]. Please allow 24 to 48 hours for response by email, depending on holidays and weekends, although we are often able to reply more quickly than that.

We also recommend that you subscribe to the community mailing lists. The mailing lists have a responsive and knowledgeable community of hundreds of developers and technical users who are located around the world. When you join the community, you will be connected to this group of people who can help you learn about SDR and respond to your technical and specific questions. Often your question can be answered quickly on the mailing lists. Each mailing list also provides an archive of all past conversations and discussions going back many years. Your question or problem may have already been addressed before, and a relevant or helpful solution may already exist in the archive.

Discussions involving the USRP hardware and the UHD software itself are best addressed through the '''usrp-users''' mailing list at [http://usrp-users.ettus.com http://usrp-users.ettus.com].

Discussions involving the use of [http://gnuradio.org/ GNU Radio] with USRP hardware and UHD software are best addressed through the '''discuss-gnuradio''' mailing list at [https://lists.gnu.org/mailman/listinfo/discussgnuradio https://lists.gnu.org/mailman/listinfo/discussgnuradio].

Discussions involving the use of [http://openbts.org/ OpenBTS®] with USRP hardware and UHD software are best addressed through the '''openbts-discuss''' mailing list at [https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss].

The support page on our website is located at [https://www.ettus.com/support https://www.ettus.com/support]. The Knowledge Base is located at [https://kb.ettus.com https://kb.ettus.com].

==Legal Considerations==
Every country has laws governing the transmission and reception of radio signals. Users are solely responsible for insuring they use their USRP system in compliance with all applicable laws and regulations. Before attempting to transmit and/or receive on any frequency, we recommend that you determine what licenses may be required and what restrictions may apply.

==Sales and Ordering Support==
If you have any non-technical questions related to your order, then please contact us by email at [mailto:orders@ettus.com orders@ettus.com], or by phone at +14086106399 (Monday-Friday, 8 AM - 5 PM, Pacific Time). Please be sure to include your order number and the serial number of your USRP.

==Terms and Conditions of Sale==
Terms and conditions of sale can be accessed online at the following link: http://www.ettus.com/legal/terms-and-conditions-of-sale

[[Category:Getting Started Guides]]

OBX

2025-09-02T20:59:23Z

DylanCaswell: /* RF Specifications */

OBX

2025-09-02T20:58:36Z

DylanCaswell:

OBX

2025-09-02T20:53:17Z

DylanCaswell: /* UBX-40/UBX-160 */

OBX

2025-09-02T20:52:51Z

DylanCaswell: /* Key Features */

OBX

2025-09-02T20:52:32Z

DylanCaswell: /* Important Notes */

OBX

2025-09-02T20:52:21Z

DylanCaswell: /* Key Component Datasheets */

OBX

2025-09-02T20:32:55Z

DylanCaswell:

'''THIS PAGE IS IN WORK - INFORMATION INVALID
'''
== Device Overview ==
The OBX 160 daughterboard is a full-duplex wideband transceiver that covers frequencies from 10 MHz to 8.4 GHz with up to 160 MHz* of instantaneous bandwidth. Coherent and phase-aligned operation across multiple OBX daughterboards enables users to explore MIMO and direction finding applications. The OBX 160 daughterboard works interchangeably with other USRP daughterboards and is compatible with the USRP X300 Series devices.

The OBX is capable of phase coherent operation, and therefore is suitable for MIMO and Phased Array applications.

== Key Features==
{|
|style="vertical-align:top"|
* Frequency Range: 10 MHz - 8.4 GHz
* Versions: 160MHz
*RF shielding
*Full duplex operation with independent TX and RX frequencies
*Synthesizer synchronization for applications requiring coherent or <br>phase-aligned operation
|[[File:OBX.jpg|250px|center]]
|[[File:OBX.X310.jpg|250px|center]]
|}

==Daughterboard Specifications==
===Features===
* 2 quadrature frontends (1 transmit, 1 receive)
** Defaults to direct conversion
** Can be used in low IF mode through lo_offset with uhd::tune_request_t
* Independent receive and transmit LO's and synthesizers
** Allows for full-duplex operation on different transmit and receive frequencies
** Can be set to use Integer-N tuning for better spur performance with uhd::tune_request_t

===Antennas===
Transmit: '''TX/RX'''

Receive: '''TX/RX''' or '''RX2'''
* '''Frontend 0:''' Complex baseband signal for selected antenna
* '''Note:''' The user may set the receive antenna to be TX/RX or RX2. However, when using a UBX board in full-duplex mode, the receive antenna will always be set to RX2, regardless of the settings.

===Gains===
* Transmit Gains: '''PGA0''', Range: 0-31.5dB
* Receive Gains: '''PGA0''', Range: 0-31.5dB

===Bandwidths===
* OBX-160: 160 MHz, RX & TX

* Note: The UBX 160 transmitter path has 160 MHz of bandwidth throughout the full frequency range of the device; the receiver path has 84 MHz of bandwidth for center frequencies from 10 MHz to 500 MHz.

===Sensors===
* '''lo_locked:''' boolean for LO lock state

===LEDs===
* '''LOCK''': Synthesizer Lock Detect
* '''TX/RX TXD''': Transmitting on TX/RX antenna port
* '''TX/RX RXD''': Receiving on TX/RX antenna port
* '''RX2 RXD''': Receiving on RX2 antenna port

==RF Specifications==

See: SPEC URL

===Input/Output Impedance===
* All RF Ports are matched to 50 Ohm with -10dB or better return loss generally. Detailed test is pending.

===Input Power Levels===
* The maximum input power for the OBX is -15 dBm.

==Hardware Specifications==

===OBX-160===
* Ettus Research recommends to always use the latest stable version of UHD
* Current Hardware Revision: 1
* Minimum version of UHD required for OBX: 3.9.0

==Environmental Specifications==
===Operating Temperature Range===
* 0-40 °C

===Operating Humidity Range===
* 10% to 90% non-condensing

==Phase Synchronization==
The OBX daughterboard is capable of phase-synchronous operation, and is recommended for phase-coherent applications. The SBX and TwinRX daughterboards are also recommended for phase-coherent applications.

If you are operating the OBX at frequencies below 1 GHz and need phase synchronization, then it is necessary to select a 20 MHz daughterboard clock rate, instead of using the default 50 MHz rate. Note that this is only required for phase synchronization below 1 GHz. The UBX can still operate below 1 GHz without setting this lower daughterboard clock rate, but it will operate without any phase synchronization capability.

If you're using a UHD program, then you can specify the lower daughterboard clock rate on the command line of the program, with <code>--args="dboard_clock_rate=20e6"</code>.

If you're using the UHD API from a C++ program, then you can include <code>"dboard_clock_rate=20e6"</code> in the device arguments parameter when first invoking <code>multi_usrp::make()</code>.

If you're using GNU Radio, then you can add <code>"dboard_clock_rate=20e6"</code> to the <code>"Device Arguments"</code> field of the properties for the UHD Sink and UHD Source blocks.

==Schematics==
===OBX===
TBD

==Key Component Datasheets==
{| class="wikitable" style="width:80%"
!Part Number
!Description
!Schematic ID (Page)
|-

|[https://datasheets.maximintegrated.com/en/ds/MAX2871.pdf MAX2871]
|Fractional/Integer-N Synthesizer/VCO
|U3 (3); U9 (5); U19 (7); U23 (9)
|-

|[http://www.analog.com/media/en/technical-documentation/evaluation-documentation/ADL5375.pdf ADL5375-05]
|Quadrature Modulator
|U22 (8)
|-

|[http://www.minicircuits.com/pdfs/LFCN-2250.pdf LFCN-2250+]
|Low Pass Filter
|F1 (3); F24 (7); F34, F35 (10)
|-

|[http://cds.linear.com/docs/en/datasheet/5510fa.pdf LTC5510]
|Active Mixer
|U15 (6)
|-

|[https://www.minicircuits.com/pdfs/LFCN-490.pdf LFCN-490+]
|Low Pass Filter
|F12 (5); F15 (6); F26 (7); F31 (9); F33, F36 (10)
|-

|[http://media.digikey.com/pdf/Data%20Sheets/Analog%20Devices%20PDFs/HMC624LP4E.pdf HMC624LP4E]
|ATTENUATOR
|U16 (6)
|-

|[http://www.rfmd.com/store/downloads/dl/file/id/29224/nbb_400_data_sheet.pdf NBB-400]
|Amplifier
|U13 (6); U30 (11)
|-

|[https://www.minicircuits.com/pdfs/PHA-1+.pdf PHA-1+]
|Amplifier
|U31 (11)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/ADA4927-1_ADA4927-2.pdf ADA4927-2]
|Differential ADC Driver
|U6 (4)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5380.pdf ADL5380]
|Quadrature Demodulator
|U8 (4)
|-

|[http://www.avagotech.com/docs/AV02-1237EN MGA-62563]
|Low Noise Amplifier
|U36 (11)
|-

|[https://www.minicircuits.com/pdfs/LFCN-1700.pdf LFCN-1700+]
|Low Pass Filter
|F41 (11)
|-

|[http://www.avagotech.com/docs/AV02-2919EN VMMK-3603]
|Low Noise Amplifier
|U34 (11)
|-

|[https://www.minicircuits.com/pdfs/LFCN-2600.pdf LFCN-2600+]
|Low Pass Filter
|F14, F17 (6)
|-

|[http://www.triquint.com/products/d/doc-a-00000518 855916]
|SAW Filter
|F16 (6)
|-

|[http://cds.linear.com/docs/en/datasheet/5510fa.pdf LTC5510]
|Active Mixer
|U15 (6); U28 (10)
|-

|[https://www.minicircuits.com/pdfs/LFCN-2600.pdf LFCN-2600+]
|Low Pass Filter
|F14, F17 (10)
|-

|[http://www.minicircuits.com/pdfs/TCM1-63AX+.pdf TCM1-63AX+]
|RF Transformer
|T1 (3); T2, T3 (4); T7 (8)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/ADA4927-1_ADA4927-2.pdf ADA4927-2]
|Differential ADC Driver
|U6 (4)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/AD8591_8592_8594.pdf AD8591]
|Operational Amplifiers
|U7 (4)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5380.pdf ADL5380]
|Quadrature Demodulator
|U8 (4)
|-

|[http://www.diodes.com/_files/datasheets/ZXTC2062E6.pdf ZXTC2062E6]
|TRANSISTORS
|Q1 (6)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/hmc624a.pdf HMC624ALP4E]
|ATTENUATOR
|U16 (6); U29 (10)
|-

|[https://www.minicircuits.com/pdfs/LFCN-800.pdf LFCN-800+]
|Low Pass Filter
|F2 (3); F25 (7)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/ADP7104.pdf ADP7104-3.3]
|CMOS LDO
|U4, U5 (3); U10, U11 (5); U20, U21 (7); U24, U25 (9); U48 (13)
|-

|[http://www.analog.com/media/en/technical-documentation/evaluation-documentation/ADL5375.pdf ADL5375-05]
|Quadrature Modulator
|U22 (8)
|-

|[http://cds.linear.com/docs/en/datasheet/5510fa.pdf LTC5510]
|Active Mixer
|U28 (10)
|-

|[http://ww1.microchip.com/downloads/en/DeviceDoc/21210G.pdf 24LC024]
|EEPROM
|U38, U39 (12)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/ADP7104.pdf ADP7104-5.0]
|CMOS LDO
|U41, U42, U43, U44, U45, U46, U47 (13)
|-

|[http://www.diodes.com/_files/datasheets/ZXTC2062E6.pdf ZXTC2062E6]
|TRANSISTORS
|Q2, Q3, Q4, Q5 (13)
|-
|}

==Mechanical Information==
===Drawings===

* [[Media:cu ettus UBX cca.pdf | PDF Format]]

* [[Media:cu ettus UBX cca.stp | STP Format]]

==RF Connectors==
* The UBX daughterboard features female SMA connectors for both the TX/RX and RX2 connectors.

==Certifications==
===RoHS===
As of December 1st, 2010 all Ettus Research products are RoHS compliant unless otherwise noted. More information can be found at [http://ettus.com/legal/rohs-information http://ettus.com/legal/rohs-information]

===China RoHS===
'''Management Methods for Controlling Pollution Caused by Electronic Information Products Regulation'''

'''Chinese Customers'''

National Instruments is in compliance with the Chinese policy on the Restriction of Hazardous Substances (RoHS) used in Electronic Information Products. For more information about the National Instruments China RoHS compliance, visit [http://www.ni.com/environment/rohs_china ni.com/environment/rohs_china].

==Certificate of Volatility==
===UBX-40/UBX-160===
* [[Media:volatility UBX CBX WBX SBX r1 1.pdf]]

==Important Notes==
*A larger 24W (6V, 4A) power supply is required when using a UBX-40 daughterboard and integrated GPS Disciplined Oscillator accessory together in a USRP2, USRP N200, or USRP N210 device.
*The UBX-160 transmitter path has 160 MHz of bandwidth throughout the full frequency range of the device; the receiver path has 84 MHz of bandwidth for center frequencies from 10 MHz to 500 MHz.

==Downloads==

[http://files.ettus.com/manual/md_fpga.html FPGA Resources]

[http://files.ettus.com/binaries/uhd_stable/ UHD Stable Binaries]

[https://github.com/EttusResearch/uhd UHD Source Code on Github]

[[Category:Hardware Resources]]

OBX

2025-09-02T20:32:25Z

DylanCaswell:

== Device Overview ==
The OBX 160 daughterboard is a full-duplex wideband transceiver that covers frequencies from 10 MHz to 8.4 GHz with up to 160 MHz* of instantaneous bandwidth. Coherent and phase-aligned operation across multiple OBX daughterboards enables users to explore MIMO and direction finding applications. The OBX 160 daughterboard works interchangeably with other USRP daughterboards and is compatible with the USRP X300 Series devices.

The OBX is capable of phase coherent operation, and therefore is suitable for MIMO and Phased Array applications.

== Key Features==
{|
|style="vertical-align:top"|
* Frequency Range: 10 MHz - 8.4 GHz
* Versions: 160MHz
*RF shielding
*Full duplex operation with independent TX and RX frequencies
*Synthesizer synchronization for applications requiring coherent or <br>phase-aligned operation
|[[File:OBX.jpg|250px|center]]
|[[File:OBX.X310.jpg|250px|center]]
|}

==Daughterboard Specifications==
===Features===
* 2 quadrature frontends (1 transmit, 1 receive)
** Defaults to direct conversion
** Can be used in low IF mode through lo_offset with uhd::tune_request_t
* Independent receive and transmit LO's and synthesizers
** Allows for full-duplex operation on different transmit and receive frequencies
** Can be set to use Integer-N tuning for better spur performance with uhd::tune_request_t

===Antennas===
Transmit: '''TX/RX'''

Receive: '''TX/RX''' or '''RX2'''
* '''Frontend 0:''' Complex baseband signal for selected antenna
* '''Note:''' The user may set the receive antenna to be TX/RX or RX2. However, when using a UBX board in full-duplex mode, the receive antenna will always be set to RX2, regardless of the settings.

===Gains===
* Transmit Gains: '''PGA0''', Range: 0-31.5dB
* Receive Gains: '''PGA0''', Range: 0-31.5dB

===Bandwidths===
* OBX-160: 160 MHz, RX & TX

* Note: The UBX 160 transmitter path has 160 MHz of bandwidth throughout the full frequency range of the device; the receiver path has 84 MHz of bandwidth for center frequencies from 10 MHz to 500 MHz.

===Sensors===
* '''lo_locked:''' boolean for LO lock state

===LEDs===
* '''LOCK''': Synthesizer Lock Detect
* '''TX/RX TXD''': Transmitting on TX/RX antenna port
* '''TX/RX RXD''': Receiving on TX/RX antenna port
* '''RX2 RXD''': Receiving on RX2 antenna port

==RF Specifications==

See: SPEC URL

===Input/Output Impedance===
* All RF Ports are matched to 50 Ohm with -10dB or better return loss generally. Detailed test is pending.

===Input Power Levels===
* The maximum input power for the OBX is -15 dBm.

==Hardware Specifications==

===OBX-160===
* Ettus Research recommends to always use the latest stable version of UHD
* Current Hardware Revision: 1
* Minimum version of UHD required for OBX: 3.9.0

==Environmental Specifications==
===Operating Temperature Range===
* 0-40 °C

===Operating Humidity Range===
* 10% to 90% non-condensing

==Phase Synchronization==
The OBX daughterboard is capable of phase-synchronous operation, and is recommended for phase-coherent applications. The SBX and TwinRX daughterboards are also recommended for phase-coherent applications.

If you are operating the OBX at frequencies below 1 GHz and need phase synchronization, then it is necessary to select a 20 MHz daughterboard clock rate, instead of using the default 50 MHz rate. Note that this is only required for phase synchronization below 1 GHz. The UBX can still operate below 1 GHz without setting this lower daughterboard clock rate, but it will operate without any phase synchronization capability.

If you're using a UHD program, then you can specify the lower daughterboard clock rate on the command line of the program, with <code>--args="dboard_clock_rate=20e6"</code>.

If you're using the UHD API from a C++ program, then you can include <code>"dboard_clock_rate=20e6"</code> in the device arguments parameter when first invoking <code>multi_usrp::make()</code>.

If you're using GNU Radio, then you can add <code>"dboard_clock_rate=20e6"</code> to the <code>"Device Arguments"</code> field of the properties for the UHD Sink and UHD Source blocks.

==Schematics==
===OBX===
TBD

==Key Component Datasheets==
{| class="wikitable" style="width:80%"
!Part Number
!Description
!Schematic ID (Page)
|-

|[https://datasheets.maximintegrated.com/en/ds/MAX2871.pdf MAX2871]
|Fractional/Integer-N Synthesizer/VCO
|U3 (3); U9 (5); U19 (7); U23 (9)
|-

|[http://www.analog.com/media/en/technical-documentation/evaluation-documentation/ADL5375.pdf ADL5375-05]
|Quadrature Modulator
|U22 (8)
|-

|[http://www.minicircuits.com/pdfs/LFCN-2250.pdf LFCN-2250+]
|Low Pass Filter
|F1 (3); F24 (7); F34, F35 (10)
|-

|[http://cds.linear.com/docs/en/datasheet/5510fa.pdf LTC5510]
|Active Mixer
|U15 (6)
|-

|[https://www.minicircuits.com/pdfs/LFCN-490.pdf LFCN-490+]
|Low Pass Filter
|F12 (5); F15 (6); F26 (7); F31 (9); F33, F36 (10)
|-

|[http://media.digikey.com/pdf/Data%20Sheets/Analog%20Devices%20PDFs/HMC624LP4E.pdf HMC624LP4E]
|ATTENUATOR
|U16 (6)
|-

|[http://www.rfmd.com/store/downloads/dl/file/id/29224/nbb_400_data_sheet.pdf NBB-400]
|Amplifier
|U13 (6); U30 (11)
|-

|[https://www.minicircuits.com/pdfs/PHA-1+.pdf PHA-1+]
|Amplifier
|U31 (11)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/ADA4927-1_ADA4927-2.pdf ADA4927-2]
|Differential ADC Driver
|U6 (4)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5380.pdf ADL5380]
|Quadrature Demodulator
|U8 (4)
|-

|[http://www.avagotech.com/docs/AV02-1237EN MGA-62563]
|Low Noise Amplifier
|U36 (11)
|-

|[https://www.minicircuits.com/pdfs/LFCN-1700.pdf LFCN-1700+]
|Low Pass Filter
|F41 (11)
|-

|[http://www.avagotech.com/docs/AV02-2919EN VMMK-3603]
|Low Noise Amplifier
|U34 (11)
|-

|[https://www.minicircuits.com/pdfs/LFCN-2600.pdf LFCN-2600+]
|Low Pass Filter
|F14, F17 (6)
|-

|[http://www.triquint.com/products/d/doc-a-00000518 855916]
|SAW Filter
|F16 (6)
|-

|[http://cds.linear.com/docs/en/datasheet/5510fa.pdf LTC5510]
|Active Mixer
|U15 (6); U28 (10)
|-

|[https://www.minicircuits.com/pdfs/LFCN-2600.pdf LFCN-2600+]
|Low Pass Filter
|F14, F17 (10)
|-

|[http://www.minicircuits.com/pdfs/TCM1-63AX+.pdf TCM1-63AX+]
|RF Transformer
|T1 (3); T2, T3 (4); T7 (8)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/ADA4927-1_ADA4927-2.pdf ADA4927-2]
|Differential ADC Driver
|U6 (4)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/AD8591_8592_8594.pdf AD8591]
|Operational Amplifiers
|U7 (4)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5380.pdf ADL5380]
|Quadrature Demodulator
|U8 (4)
|-

|[http://www.diodes.com/_files/datasheets/ZXTC2062E6.pdf ZXTC2062E6]
|TRANSISTORS
|Q1 (6)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/hmc624a.pdf HMC624ALP4E]
|ATTENUATOR
|U16 (6); U29 (10)
|-

|[https://www.minicircuits.com/pdfs/LFCN-800.pdf LFCN-800+]
|Low Pass Filter
|F2 (3); F25 (7)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/ADP7104.pdf ADP7104-3.3]
|CMOS LDO
|U4, U5 (3); U10, U11 (5); U20, U21 (7); U24, U25 (9); U48 (13)
|-

|[http://www.analog.com/media/en/technical-documentation/evaluation-documentation/ADL5375.pdf ADL5375-05]
|Quadrature Modulator
|U22 (8)
|-

|[http://cds.linear.com/docs/en/datasheet/5510fa.pdf LTC5510]
|Active Mixer
|U28 (10)
|-

|[http://ww1.microchip.com/downloads/en/DeviceDoc/21210G.pdf 24LC024]
|EEPROM
|U38, U39 (12)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/ADP7104.pdf ADP7104-5.0]
|CMOS LDO
|U41, U42, U43, U44, U45, U46, U47 (13)
|-

|[http://www.diodes.com/_files/datasheets/ZXTC2062E6.pdf ZXTC2062E6]
|TRANSISTORS
|Q2, Q3, Q4, Q5 (13)
|-
|}

==Mechanical Information==
===Drawings===

* [[Media:cu ettus UBX cca.pdf | PDF Format]]

* [[Media:cu ettus UBX cca.stp | STP Format]]

==RF Connectors==
* The UBX daughterboard features female SMA connectors for both the TX/RX and RX2 connectors.

==Certifications==
===RoHS===
As of December 1st, 2010 all Ettus Research products are RoHS compliant unless otherwise noted. More information can be found at [http://ettus.com/legal/rohs-information http://ettus.com/legal/rohs-information]

===China RoHS===
'''Management Methods for Controlling Pollution Caused by Electronic Information Products Regulation'''

'''Chinese Customers'''

National Instruments is in compliance with the Chinese policy on the Restriction of Hazardous Substances (RoHS) used in Electronic Information Products. For more information about the National Instruments China RoHS compliance, visit [http://www.ni.com/environment/rohs_china ni.com/environment/rohs_china].

==Certificate of Volatility==
===UBX-40/UBX-160===
* [[Media:volatility UBX CBX WBX SBX r1 1.pdf]]

==Important Notes==
*A larger 24W (6V, 4A) power supply is required when using a UBX-40 daughterboard and integrated GPS Disciplined Oscillator accessory together in a USRP2, USRP N200, or USRP N210 device.
*The UBX-160 transmitter path has 160 MHz of bandwidth throughout the full frequency range of the device; the receiver path has 84 MHz of bandwidth for center frequencies from 10 MHz to 500 MHz.

==Downloads==

[http://files.ettus.com/manual/md_fpga.html FPGA Resources]

[http://files.ettus.com/binaries/uhd_stable/ UHD Stable Binaries]

[https://github.com/EttusResearch/uhd UHD Source Code on Github]

[[Category:Hardware Resources]]

OBX Getting Started Guides

2025-09-02T20:25:46Z

DylanCaswell: Created page with "==Kit Contents== * OBX Daughterboard * OBX Installation Hardware (Washers, Nuts, Screws, Torx Key) * 2x SMA F to SMPM F Cables * SMPM Insertion/Extraction Tool * Standoff Remo..."

==Kit Contents==
* OBX Daughterboard
* OBX Installation Hardware (Washers, Nuts, Screws, Torx Key)
* 2x SMA F to SMPM F Cables
* SMPM Insertion/Extraction Tool
* Standoff Removal Wrench
* Safety, Environmental, and Regulatory Information (SERI)
* OBX QR Code Weblink Insert (Links to this page)
{|
|[[File:OBX.jpg|250px|center]]
|[[File:OBX.X310.jpg|250px|center]]
|}

==USRP Compatibility==

===OBX-160===
* X Series only

==Hardware Setup==
Installation instructions pending

==Proper Care and Handling==
All Ettus Research products are individually tested before shipment. The UBX is guaranteed to be functional at the time it is received by the customer. Improper use or handling of the UBX can easily cause the device to become non-functional. Listed below are some examples of actions which can prevent damage to the unit:

*Never allow metal objects to touch the circuit board while powered.
*Always properly terminate the transmit port with an antenna or 50Ω load.
*Always handle the board with proper anti-static methods.
*Never allow the board to directly or indirectly come into contact with any voltage spikes.
*Never allow any water, or condensing moisture, to come into contact with the boards.
*Always use caution with FPGA, firmware, or software modifications.
{|
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |Never apply more than -15 dBm of power into any RF input.
|-
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |Always use at least 30dB attenuation if operating in loopback configuration
|-
|}

==Technical Support and Community Knowledge Base==
Technical support for USRP hardware is available through email only. If the product arrived in a nonfunctional state or you require technical assistance, please contact [mailto:support@ettus.com support@ettus.com]. Please allow 24 to 48 hours for response by email, depending on holidays and weekends, although we are often able to reply more quickly than that.

We also recommend that you subscribe to the community mailing lists. The mailing lists have a responsive and knowledgeable community of hundreds of developers and technical users who are located around the world. When you join the community, you will be connected to this group of people who can help you learn about SDR and respond to your technical and specific questions. Often your question can be answered quickly on the mailing lists. Each mailing list also provides an archive of all past conversations and discussions going back many years. Your question or problem may have already been addressed before, and a relevant or helpful solution may already exist in the archive.

Discussions involving the USRP hardware and the UHD software itself are best addressed through the '''usrp-users''' mailing list at [http://usrp-users.ettus.com http://usrp-users.ettus.com].

Discussions involving the use of [http://gnuradio.org/ GNU Radio] with USRP hardware and UHD software are best addressed through the '''discuss-gnuradio''' mailing list at [https://lists.gnu.org/mailman/listinfo/discussgnuradio https://lists.gnu.org/mailman/listinfo/discussgnuradio].

Discussions involving the use of [http://openbts.org/ OpenBTS®] with USRP hardware and UHD software are best addressed through the '''openbts-discuss''' mailing list at [https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss].

The support page on our website is located at [https://www.ettus.com/support https://www.ettus.com/support]. The Knowledge Base is located at [https://kb.ettus.com https://kb.ettus.com].

==Legal Considerations==
Every country has laws governing the transmission and reception of radio signals. Users are solely responsible for insuring they use their USRP system in compliance with all applicable laws and regulations. Before attempting to transmit and/or receive on any frequency, we recommend that you determine what licenses may be required and what restrictions may apply.

==Sales and Ordering Support==
If you have any non-technical questions related to your order, then please contact us by email at [mailto:orders@ettus.com orders@ettus.com], or by phone at +14086106399 (Monday-Friday, 8 AM - 5 PM, Pacific Time). Please be sure to include your order number and the serial number of your USRP.

==Terms and Conditions of Sale==
Terms and conditions of sale can be accessed online at the following link: http://www.ettus.com/legal/terms-and-conditions-of-sale

[[Category:Getting Started Guides]]

File:OBX.X310.jpg

2025-09-02T20:24:18Z

DylanCaswell:

File:OBX.jpg

2025-09-02T20:23:43Z

DylanCaswell:

OBX

2025-09-02T15:56:28Z

DylanCaswell: Created page with "Placeholder"

Placeholder

USRP X410/X440 Getting Started Guide

2025-03-28T13:09:46Z

DylanCaswell: /* eMMC Storage */

==Kit Contents==
===X4x0===
{|
|style="vertical-align:top"|
* NI Ettus USRP X410 or X440
* DC Power Supply (12V, 20A)
* 1 Gigabit Ethernet Cat-5e Cable (3m)
* USB-A to USB-C Cable (1m)
* Getting Started Guide URL (QR Code)
* Safety, Environmental, and Regulatory Information
||[[File:X410.jpg|450px|center]]
||[[File:X440.jpg|450px|center]]
|}

==USRP X440 Design Considerations==
* https://kb.ettus.com/About_Sampling_Rates_and_Master_Clock_Rates_for_the_USRP_X440

==You Will Need==
* For Network Mode: A host computer with an available 1 or 10 Gigabit Ethernet interface for sample streaming. In addition to the Ethernet interface used for sampling streaming, your host computer will require a separate 1 Gigabit Ethernet interface for command and control streaming.

* For Stand-Alone Embedded Mode: A host computer with an available 1 Gigabit Ethernet port or a USB 2.0 port to remotely access the embedded Linux operating system running on ARM CPU.

==Proper Care and Handling==

All Ettus Research products are individually tested before shipment. The USRP is guaranteed to be functional at the time it is received by the customer. Improper use or handling of the USRP can cause the device to become non-functional. Take the following precautions to prevent damage to the unit.

* Never allow metal objects to touch the circuit board while powered.
* Always properly terminate the transmit port with an antenna or 50Ω load.
* Always handle the board with proper anti-static methods.
* Never allow the board to directly or indirectly come into contact with any voltage spikes.
* Never allow any water or condensing moisture to come into contact with the device.
* Always use caution with FPGA, firmware, or software modifications.

{|
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |X410: Never apply more than +14 dBm continuous <=3GHz, +17 dBm continuous >3GHz, or +20dBm more than 5 minutes >3GHz of power into any RF input.
|-
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |X440: Never apply more than +13 dBm continuous <=2.5GHz, +17 dBm continuous between 2.5GHz and 3.6 GHz, or +20dBm continuous between 3.6 GHz and 4 GHz of power into any RF input.
|-
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |X410: Always use at least 30dB attenuation if operating in loopback configuration.
|-
|}

==Install and Setup the Software Tools on Your Host Computer==
In order to use your Universal Software Radio Peripheral (USRP™), you must have the software tools correctly installed and configured on your host computer. The easiest way to install USRP Hardware Driver (UHD) is by getting a binary installer package for your operating system as described in the UHD manual about [https://files.ettus.com/manual/page_install.html Binary Installation]. If no binary packages are available for your operating system or you want to modify the sources by yourself, a step-by-step guide is available at the Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on [[Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on Linux|Linux]], [[Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on OS X|OS X]] and [[Building and Installing the USRP Open Source Toolchain (UHD and GNU Radio) on Windows|Windows]] Application Notes.

To find the latest release of UHD, see the UHD repository at https://github.com/EttusResearch/uhd.

The USRP X410 requires UHD version 4.1 or later.
The USRP X440 requires UHD version 4.5 or later.

'''When you receive a brand-new device, it is strongly recommended that you download the latest filesystem image from the Ettus Research website update the unit. It is not recommended that you use the filesystem from the factory as-is. Instructions on downloading the latest filesystem image and updating it is listed below.'''

'''Note that if you are operating the device in Network Mode, the version of UHD running on the host computer and the USRP X4x0 must match.'''

==Assembling the X4x0==
Inside the kit you will find the X4x0 and an X4x0 power supply. Plug these in, connect the 1GbE RJ45 interface to your network, and power on the device by pressing the power button.

==The STM32 Microcontroller==

The STM32 microcontroller (also referred to as the "SCU") controls various low-level features of the X4x0 series motherboard: It controls the power sequencing, reads out fan speeds and some of the temperature sensors. It is connected to the RFSoC via an I2C bus. It is running software based on Chromium EC.

It is possible to log into the STM32 using the serial interface (see Connecting to the Microcontroller). This will allow certain low-level controls, such as remote power cycling should the CPU have become unresponsive for whatever reason.

===Updating the SCU===

The writable SCU image file is stored on the filesystem under /lib/firmware/ni/ec-titanium-revX.RW.bin (where X is a revision compatibility number). To update, simply replace the .bin file with the updated version and reboot.

==eMMC Storage==

The main non-volatile storage of the USRP is an eMMC:

* USRP X410: 16 GB (Module Revision H or earlier) or 32 GB (Module Revision J and later)

* USRP X440: 16 GB (Module Revision D or earlier) or 32 GB (Module Revision E and later)

This storage can be made accessible as a USB Mass Storage device through the USB-OTG connector on the back panel.

The entire root file system (Linux kernel, libraries) and any user data are stored on the eMMC. It is partitioned into four partitions:

Boot partition (contains the bootloader). This partition usually does not require modification.
A data partition, mounted in /data. This is the only partition that is not erased during file system updates.
Two identical system partitions (root file systems). These contain the operating system and the home directory (anything mounted under / that is not the data or boot partition). The reason there are two of these is to enable remote updates: An update running on one partition can update the other one without any effect to the currently running system. Note that the system partitions are erased during updates and are thus unsuitable for permanently storing information.
Note: It is possible to access the currently inactive root file system by mounting it. After logging into the device using serial console or SSH (see the following two sections), run the following commands:

<pre>
$ mkdir temp

$ mount /dev/mmcblk0p3 temp # This assumes mmcblk0p3 is currently not mounted

$ ls temp # You are now accessing the idle partition:

bin data etc lib media proc sbin tmp usr
boot dev home lost+found mnt run sys uboot var
</pre>

The device node in the mount command might differ, depending on which partition is currently already mounted.

==USB Access to eMMC==

While Mender should be used for routine filesystem updates (see Updating Filesystems), it is also possible to access the X4x0's internal eMMC from an external host over USB. This allows accessing or modifying the filesystem, as well as the ability to flash the device with an entirely new filesystem.

In order to do so, you'll need an external computer with two USB ports, and two USB cables to connect the computer to your X4x0. The instructions below assume a Linux host.

First, connect to the APU serial console at a baud rate of 115200. Boot the device, and stop the boot sequence by typing noautoboot at the prompt. Then, run the following command in the U-boot command prompt:

<code>ums 0 mmc 0</code>

This will start the USB mass storage gadget to expose the eMMC as a USB mass storage device. You should see a spinning indicator on the console, which indicates the gadget is active.

Next, connect your external computer to the X4x0's USB to PS port using an OTG cable. Your computer should recognize the X4x0 as a mass storage device, and you should see an entry in your kernel logs (dmesg) that looks like this:

<pre>
usb 3-1: New USB device found, idVendor=3923, idProduct=7a7d, bcdDevice= 2.23
usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 3-1: Product: USB download gadget
usb 3-1: Manufacturer: National Instruments
sd 6:0:0:0: [sdc] 30932992 512-byte logical blocks: (15.8 GB/14.8 GiB)
sdc: sdc1 sdc2 sdc3 sdc4
sd 6:0:0:0: [sdc] Attached SCSI removable disk
</pre>

The exact output will depend on your machine, but from this log you can see that the X4x0 was recognized and /dev/sdc is the block device representing the eMMC, with 4 partitions detected (see eMMC Storage for details on the partition layout).

It is now possible to treat the X4x0's eMMC as you would any other USB drive: the individual partitions can be mounted and accessed, or the entire block device can be read/written.

Once you're finished accessing the device over USB, the u-boot gadget may be stopped by hitting Ctrl-C at the APU serial console.

== Flashing the eMMC ==

Once the X4x0's eMMC is accessible over USB, it's possible to write the filesystem image and thus change the device's filesystem. You can obtain the latest filesystem image by running:

<code>uhd_images_downloader -t sdimg -t x4xx</code>

The output of this command will indicate where the downloaded images were put, or specify a custom location using using the <code>-i INSTALL_LOCATION</code> argument.

There are 2 ways to write the image to the X4x0's eMMC: using <code>dd</code> and <code>bmaptool</code>. Run one of the following commands, replacing <code>/dev/sdX</code> with the block device of the X4x0's eMMC (found in the device's kernel log or by running <code>lsblk</code>). Take care to use the correct block device or else you might overwrite the wrong drive!

<code>sudo dd if=/path/to/usrp_x4xx_fs.sdimg of=/dev/sdX bs=1M</code>

<code>sudo bmaptool copy --bmap /path/to/usrp_x4xx_fs.sdimg.bmap /path/to/usrp_x4xx_fs.sdimg /dev/sdX</code>

The former is generally preferred as it will always work, even if it slower than the latter.

==Using a USRP X4x0 from UHD==
Like any other USRP, all X4x0 USRPs are controlled by the UHD software. To integrate a USRP X4x0 into your C++ application, you would generate a UHD device in the same way you would for any other USRP:

<code>auto usrp = uhd::usrp::multi_usrp::make("type=x4xx");</code>

For a list of which arguments can be passed into make(), see Section Device Arguments.

==Updating Filesystems==

Mender is a third-party software that enables remote updating of the root file system without physically accessing the device (see also the [https://mender.io/ Mender website]). Mender can be executed locally on the device, or a Mender server can be set up which can be used to remotely update an arbitrary number of USRP devices. Mender servers can be self-hosted, or hosted by Mender (see mender.io for pricing and availability).

When updating the file system using Mender, the tool will overwrite the root file system partition that is not currently mounted (note: the onboard flash storage contains two separate root file system partitions, only one is ever used at a single time). Any data stored on that partition will be permanently lost, including the currently loaded FPGA image. After updating that partition, it will reboot into the newly updated partition. Only if the update is confirmed by the user, the update will be made permanent. This means that if an update fails, the device will be always able to reboot into the partition from which the update was originally launched (which presumably is in a working state). Another update can be launched now to correct the previous, failed update, until it works.

To obtain the file system Mender image (these are files with a <code>.mender</code> suffix), run the following command on the host computer with Internet access:

$ sudo uhd_images_downloader -t mender -t x4xx --yes

NOTE: In the output of the command, the folder destination where the images are saved is printed out.

Next, you will need to copy this Mender file system image to the USRP X4xx. This can be done with the Linux utility <code>scp</code>.

$ scp /usr/local/share/uhd/images/usrp_x4xx_fs.mender root@192.168.1.51:~/.

Note: The path and IP may different for your configuration, the command above assumes you're using the default installation path of <code>/usr/local</code> and that the X4xx's IP is <code>192.168.1.51</code>.

After copying the Mender file system image to the X4xx, connect to the X4xx using either the Serial Console, or via SSH to gain shell access.

On the X4xx, run <code>mender install /path/to/latest.mender</code> to update the file system:

$ mender install /home/root/usrp_x4xx_fs.mender

The artifact can also be stored on a remote server:
$ mender install <nowiki>http://server.name/path/to/latest.mender</nowiki>

This procedure will take a few minutes to complete. After mender has logged a successful update, reboot the device:
$ reboot

If the reboot worked, and the device seems functional, commit the changes so that the boot loader knows to permanently boot into this partition:
$ mender -commit

To identify the currently installed Mender artifact from the command line, the following file can be queried on the X4x0:
$ cat /etc/mender/artifact_info

If you are using a Mender server, the updates can be initiated from a web dashboard. From there, you can start the updates without having to log into the device, and you can update groups of USRPs with a few clicks in a web GUI. The dashboard can also be used to inspect the state of USRPs. This is a simple way to update groups of rack-mounted USRPs with custom file systems.

If you are running a hosted server, the updates can be initiated from a web dashboard. From there, you can start the updates without having to log into the device, and can update groups of USRPs with a few clicks in a web GUI. The dashboard can also be used to inspect the state of USRPs. This is a simple way to update groups of rack-mounted USRPs with custom file systems.

==Network Interfaces==
The Ettus USRP X4x0 has various network interfaces:

eth0: RJ45 port.

The RJ45 port comes up with a default configuration of DHCP, that will request a network address from your DHCP server (if available on your network). This interface is agnostic of FPGA image flavor.

int0: internal interface for network communication between the embedded ARM processor and FPGA.

The internal network interface is configured with a static address: 169.254.0.1/24. This interface is agnostic of FPGA image flavor.

sfpX [, sfpX_1, sfpX_2, sfpX_3]: QSFP28 network interface(s), up-to four (one per lane) based on implemented protocol.

Each QSFP28 port has four high-speed transceiver lanes. Therefore, depending on the FPGA image flavor, up-to four different network interfaces may exist per QSFP28 port, using the sfpXfor the first lane, and sfpX_1-3 for the other three lanes. Each network interface has a default static IP address. Note that for multi-lane protocols, such as 100 GbE, a single interface is used (sfpX).
The configuration files for these network interfaces are stored in: <code>/data/network/</code>

{| class="wikitable"
|-
! Interface Name
! Description
! Default Configuration
! Configuration File
! Example: X4_200/X4_400 FPGA image
|-
| eth0
| RJ45
| style="vertical-align:middle; background-color:#FFF;" | DHCP
| style="vertical-align:middle; background-color:#FFF;" | eth0.network
| DHCP
|-
| int0
| Internal
| style="vertical-align:middle; background-color:#FFF;" | 169.254.0.1/24
| style="vertical-align:middle; background-color:#FFF;" | int0.network
| style="vertical-align:middle; background-color:#FFF;" | 169.254.0.1/24
|-
| sfp0
| QSFP28 0 (4-lanes interface or lane 0)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.10.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.10.2/24
|-
| style="background-color:#FFF;" | sfp0_1
| QSFP28 0 (lane 1)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.11.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0_1.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.11.2/24
|-
| style="background-color:#FFF;" | sfp0_2
| QSFP28 0 (lane 2)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.12.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0_2.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.12.2/24
|-
| sfp0_3
| QSFP28 0 (lane 3)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.13.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0_3.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.13.2/24
|-
| sfp1
| QSFP28 1 (4-lanes interface or lane 0)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.20.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
| sfp1_1
| QSFP28 1 (lane 1)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.21.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1_1.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
| style="background-color:#FFF;" | sfp1_2
| QSFP28 1 (lane 2)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.22.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1_2.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
| style="background-color:#FFF;" | sfp1_3
| QSFP28 1 (lane 3)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.23.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1_3.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
|}

==Network Connectivity==
Once the X4x0 has booted, determine the IP address and verify network connectivity by running uhd_find_devices on the host computer:

X410:
<pre>
$ uhd_find_devices

-- UHD Device 0

Device Address:
serial: 1234ABC
addr: 10.2.161.10
claimed: False
mgmt_addr: 10.2.161.10
product: x410
type: x4xx
</pre>

X440:
<pre>
$ uhd_find_devices

-- UHD Device 0

Device Address:
serial: 1234ABC
addr: 10.2.161.10
claimed: False
mgmt_addr: 10.2.161.10
product: x440
type: x4xx
</pre>

By default, an X4x0 will use DHCP to attempt to find an address.

At this point, you should run:

<code>uhd_usrp_probe --args addr=<IP address></code>
to ensure functionality of the device.

Note: If you receive the following error:

<code>Error: RuntimeError: Graph edge list is empty for rx channel 0</code>
then you will need to download a UHD-compatible FPGA as described in Updating the FPGA or using the following command (it assumes that FPGA images have been downloaded previously using uhd_images_downloader, or that the command is run on the device itself):

X410:
<code>uhd_image_loader --args type=x4xx,addr=<ip address>,fpga=X4_200</code>

X440:
<code>uhd_image_loader --args type=x4xx,addr=<ip address>,fpga=X4_400</code>

When running on the device, use <code>127.0.0.1</code> as the IP address.

You can now use existing UHD examples or applications (such as rx_sample_to_file, rx_ascii_art_dft, or tx_waveforms) or other UHD-compatible applications to start receiving and transmitting with the device.

See Network Interfaces for further details on the various network interfaces available on the X4x0.

===Network Status LEDs===
The Ettus USRP X4x0 is equipped with status LEDs for its network-capable ports: RJ45 and QSFP28s, see RJ45 LED Behavior and QSFP28 LED Behavior accordingly.

====RJ45 LED Behavior====
The RJ45 port has two independent LEDs: green (right) and yellow (left). The table below summarizes the LEDs' behavior. Note that link speed indication is not currently supported.

{| class="wikitable"
|- style="font-weight:bold; text-align:center; vertical-align:middle;"
! Link / Activity
! Green LED
! Yellow LED
|-
| style="vertical-align:middle; background-color:#FFF;" | No Link
| Off
| Off
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / No Activity
| On
| Off
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / Activity
| On
| Blinking
|}

====QSFP28 LED Behavior====
Each QSFP28 connector has four LEDs, one for each high-speed transceiver lane. The table below summarizes the LEDs' behavior, note that for multi-lane protocols, such as 100 GbE, the corresponding LEDs are ganged together. Within the same image, multiple speeds on the same port (e.g., both 10 GbE and 100 GbE) are not supported, therefore link speed indication is not supported.

{| class="wikitable"
|- style="font-weight:bold; text-align:center; vertical-align:middle;"
! Link / Activity
! QSFP28 LED (4 Total)
|-
| style="vertical-align:middle; background-color:#FFF;" | No Link
| Off
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / No Activity
| Green (solid)
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / Activity
| Amber (blinking)
|}

==Security-related Settings==
The X4x0 ships without a root password set. It is possible to ssh into the device by simply connecting as root, and thus gaining access to all subsystems. To set a password, run the command

<code>$ passwd</code>
on the device.

==Serial Connection==
It is possible to gain access to the device using a serial terminal emulator. To do so, the USB debug port needs to be connected to a separate computer to gain access. Most Linux, OSX, or other Unix flavors have a tool called 'screen' which can be used for this purpose, by running the following command:

<code>$ sudo screen /dev/ttyUSB2 115200</code>
In this command, we prepend 'sudo' to elevate user privileges (by default, accessing serial ports is not available to regular users), we specify the device node (in this case, /dev/ttyUSB2), and the baud rate (115200).

The exact device node depends on your operating system's driver and other USB devices that might be already connected. Modern Linux systems offer alternatives to simply trying device nodes; instead, the OS might have a directory of symlinks under /dev/serial/by-id:

<pre>$ ls /dev/serial/by-id
usb-Digilent_Digilent_USB_Device_2516351DDCC0-if02-port0
usb-Digilent_Digilent_USB_Device_2516351DDCC0-if03-port0
</pre>

Note: Exact names depend on the host operating system version and may differ.

The first (with the if02 suffix) connects to the STM32 microcontroller (SCU), whereas the second (with the if03 suffix) connects to Linux running on the RFSoC APU.

<code>$ sudo screen /dev/serial/by-id/usb-Digilent_Digilent_USB_Device_2516351DDCC0-if03-port0 115200</code>
After entering the username root (no password is set by default), you should be presented with a shell prompt similar to the following:

<code>root@ni-x4xx-1234ABC:~#</code>
On this prompt, you can enter any Linux command available. Using the default configuration, the serial console will also show all kernel log messages (unlike when using SSH, for example), and give access to the boot loader (U-boot prompt). This can be used to debug kernel or bootloader issues more efficiently than when logged in via SSH.

==Connecting to the Microcontroller==
The microcontroller (which controls the power sequencing, among other things) also has a serial console available. To connect to the microcontroller, use the other UART device. In the example above:

<code>$ sudo screen /dev/serial/by-id/usb-Digilent_Digilent_USB_Device_2516351DDCC0-if02-port0 115200</code>

It provides a very simple prompt. The command 'help' will list all available commands. A direct connection to the microcontroller can be used to hard-reset the device without physically accessing it and other low-level diagnostics. For example, running the command reboot will emulate a reset button press, resetting the state of the device, while the command powerbtn will emulate a power button press, turning the device back on again.

==SSH Connection==
The USRP X4x0 has two network connections: The dual QSFP28 ports, and an RJ45 connector. The latter is by default configured by DHCP; by plugging it into into 1 Gigabit switch on a DHCP-capable network, it will get assigned an IP address and thus be accessible via ssh.

In case your network setup does not include a DHCP server, refer to the section Serial Connection. A serial login can be used to assign an IP address manually.

After the device obtained an IP address you can log in from a Linux or OSX machine by typing:

<code>$ ssh root@ni-x4xx-1234ABC # Replace with your actual device name!</code>
Depending on your network setup, using a .local domain may work:

<code>$ ssh root@ni-x4xx-1234ABC.local</code>
Of course, you can also connect to the IP address directly if you know it (or set it manually using the serial console).

Note: The device's hostname is derived from its serial number by default (<code>ni-x4xx-$SERIAL</code>). You can change the hostname by creating the file <code>/data/network/hostname</code>, saving the desired hostname in it, then rebooting.

On Microsoft Windows, the connection can be established using a tool such as PuTTY, by selecting a username of root without password.

Like with the serial console, you should be presented with a prompt like the following:

<code>root@ni-x4xx-1234ABC:~#</code>

== Autoboot ==

The USRP X4x0 can be configured to power on and boot automatically when power is applied. This setting can be controlled using the <code>eeprom-set-autoboot</code> script. This script is executed directly on the USRP X4x0. To enable autoboot, run <code>eeprom-set-autoboot on</code>; to disable autoboot, run <code>eeprom-set-autoboot off</code>.

==Updating the FPGA==

The FPGA can be updated simply using uhd_image_loader:

<code>uhd_image_loader --args type=x4xx,addr=<IP address of device> --fpga-path <path to .bit></code>
or

<code>uhd_image_loader --args type=x4xx,addr=<IP address of device>,fpga=FPGA_TYPE</code>
A UHD install will likely have pre-built images in /usr/share/uhd/images/. Up-to-date images can be downloaded using the uhd_images_downloader script:

<code>uhd_images_downloader</code>
will download images into /usr/share/uhd/images/ (the path may differ, depending on how UHD was installed).

Also note that the USRP already ships with compatible FPGA images on the device - these images can be loaded by SSH'ing into the device and running:

X410:
<code>uhd_image_loader --args type=x4xx,mgmt_addr=127.0.0.1,fpga=X4_200</code>

X440:
<code>uhd_image_loader --args type=x4xx,mgmt_addr=127.0.0.1,fpga=X4_400</code>

==FPGA Image Flavors==
Unlike the USRP X310 or other third-generation USRP devices, the FPGA image flavors do not only encode how the QSFP28 connectors are configured, but also which master clock rates are available. This is because the data converter configuration is part of the FPGA image (the ADCs/DACs on the X4x0 are on the same die as the FPGA). The image flavors consist of two short strings, separated by an underscore, e.g. X4_200 (X410) or X4_400 (X440) is an image flavor which contains 4x 10 GbE, and can handle an analog bandwidth of 200 MHz or 400 MHz respectively. The first two characters describe the configuration of the QSFP28 ports: 'X' stands for 10 GbE, 'C' stands for 100 GbE. For details see [https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_updating_fpga_types FPGA Image Flavor] in the [https://files.ettus.com/manual USRP Hardware Driver and USRP Manual].

The analog bandwidth determines the available master clock rates.

X410: As of UHD 4.1, only the X4_200 image is shipped with UHD, which allows a 245.76 MHz or 250 MHz master clock rate. With UHD 4.2, the CG_400 image was added allowing for 491.52 MHz and 500 MHz master clock rates. With UHD 4.5, the UC_200 image (245.76 MHz and 250 MHz master clock rate) was added.

X440: As of UHD 4.5, UHD ships with X4_400, X4_1600, CG_400 and CG_1600 images. The X4_400 and CG_400 images allow master clock rates between 125 MHz and 512 MHz and the usage of all 8 channels while the X4_1600 and CG_1600 images allow master clock rates between 125 MHz and 2048 MHz but only the usage of channels 0 and 4.

Any other images are considered experimental (unsupported).

==Device Arguments==

{| class="wikitable" style="vertical-align:middle;"
|- style="font-weight:bold; text-align:center;"
! Key
! Description
! Example Value
|-
| addr
| IPv4 address of primary SFP+ port to connect to.
| addr=192.168.30.2
|-
| second_addr
| IPv4 address of secondary SFP+ port to connect to.
| second_addr=192.168.40.2
|-
| mgmt_addr
| IPv4 address or hostname to which to connect the RPC client. Defaults to `addr'.
| mgmt_addr=ni-sulfur-311FE00
|-
| find_all
| When using broadcast, find all devices, even if unreachable via CHDR.
| find_all=1
|-
| master_clock_rate
| Master Clock Rate in Hz.
| master_clock_rate=250e6
|-
| converter_rate
| Converter Rate in Hz. Only X440 and together with master_clock_rate.
| master_clock_rate=250e6,converter_rate=1000e6
|-
| serialize_init
| Force serial initialization of daughterboards.
| serialize_init=1
|-
| skip_init
| Skip the initialization process for the device.
| skip_init=1
|-
| time_source
| Specify the time (PPS) source.
| time_source=internal
|-
| clock_source
| Specify the reference clock source.
| clock_source=internal
|-
| ref_clk_freq
| Specify the external reference clock frequency, default is 10 MHz.
| ref_clk_freq=20e6
|-
| discovery_port
| Override default value for MPM discovery port.
| discovery_port=49700
|-
| rpc_port
| Override default value for MPM RPC port.
| rpc_port=49701
|}

This is only a subset of the existing device arguments. For a complete list please consult the [https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_usage_args UHD user manual of the X4x0 device series].

==GPS==

The USRP X4x0 includes a Jackson Labs LTE-Lite GPS module. Its antenna port is on the rear panel. When the X4x0 has access to GPS satellite signals, it can use this module to read out the current GPS time and location as well as to discipline an onboard OCXO.

To use the GPS as a clock and time reference, set the device arguments <code>time_source</code> and <code>clock_source</code> to <code>gpsdo</code>.

Note the GPS module is not enabled when the clock source is not set to <code>gpsdo</code>.

Its power-on status can be queried using the <code>gps_enabled</code> GPS sensor. When disabled, none of the sensors will return useful
(if any) values.

Note that acquiring a GPS lock can take some time after enabling the GPS, so if a UHD application is enabling the GPS dynamically, it might take some time before a GPS lock is reported.

To set the clock source and time source dynamically, see the following code:

<pre>
// Set clock/time individually:
usrp->set_clock_source("gpsdo");
usrp->set_time_source("gpsdo");
// This is equivalent to the previous commands, but faster, as it sets
// both settings simultaneously and avoids duplicating settings that are shared
// between these calls.
usrp->set_sync_source("clock_source=gpsdo,time_source=gpsdo");
</pre>

==Front-Panel Programmable GPIOs==

The USRP X4x0 has two HDMI front-panel connectors, which are connected to the FPGA. For a
description of the GPIO control API, see the
[https://files.ettus.com/manual/page_x400_gpio_api.html USRP X4x0 GPIO UHD Manual Entry],
[https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_usage_gpio the USRP X4x0 Series Manual],
the [https://files.ettus.com/manual/page_zbx.html#zbx_atr ZBX ATR section] (X410) and the
[https://files.ettus.com/manual/page_fbx.html#fbx_atr FBX ATR section] (X440).

==Subdev Specifications==

The RF ports on the front panel of the X410 + ZBX correspond to the following subdev specifications:

{| class="wikitable"
|-
! Label
! style="text-align:center; vertical-align:middle; font-weight:bold;" | Subdev Spec
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 0
| A:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 1
| A:1
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 0
| B:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 1
| B:1
|}

The RF ports on the front panel of the X440 + FBX correspond to the following subdev specifications (for xx_400 FPGA images):

{| class="wikitable"
|-
! Label
! style="text-align:center; vertical-align:middle; font-weight:bold;" | Subdev Spec
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 0
| A:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 1
| A:1
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 2
| A:2
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 3
| A:3
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 0
| B:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 1
| B:1
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 2
| B:2
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 3
| B:3
|}

When using a xx_1600 FPGA image on X440, only A:0 and B:0 are available.

The subdev spec slot identifiers "A" and "B" are not reflected on the front panel. They were set to match valid subdev specifications of previous USRPs, maintaining backward compatibility.

These values can be used for uhd::usrp::multi_usrp::set_rx_subdev_spec() and uhd::usrp::multi_usrp::set_tx_subdev_spec() as with other USRPs.

==Rear Panel Status LEDs==

The USRP X4x0 is equipped with four LEDs located on the device's rear panel. Each LED supports four different states: Off, Green, Red, and Amber. One LED (PWR) indicates the device's power state (see Power LED below). The other three LEDs (LED 0, LED 1, and LED 2) are user-configurable, different behaviors are supported for each of these LEDs (see User-configurable LEDs below).

[[File:x4xx_rearpanel_status_leds.png|125px]]

===X4x0 Rear Panel Status LEDs===
Power LED
The USRP X4x0's PWR LED is reserved to visually indicate the user the device's power state. Power LED Behavior describes what each LED state represents.

===Power LED Behavior===

{| class="wikitable" style="background-color:#FFF;"
|- style="font-weight:bold; text-align:center;"
! PWR LED State
! style="vertical-align:middle;" | Meaning
|- style="vertical-align:middle;"
| Off
| No power is applied
|- style="vertical-align:middle;"
| Amber
| Power is good but X4x0 is powered off
|- style="vertical-align:middle;"
| Green
| Power is good and X4x0 is powered on
|- style="vertical-align:middle;"
| Red
| Power error state
|}

===User-configurable LEDs===
The USRP X4x0's user-configurable rear panel status LEDs (LED 0, LED 1, and LED 2) allow the user to have visual indication of various device conditions. Supported LED Behaviors provides a complete list of the supported behaviors for each user-configurable LED. By default, these LEDs are configured as described in LEDs Default Behavior.

The user may alter the default LEDs behavior either temporarily or persistently, see the Temporarily change the LED Behavior or Persistently in the UHD manual to change the LED Behavior accordingly.

https://files.ettus.com/manual/page_usrp_x4xx.html

==Technical Support and Community Knowledge Base==
Technical support for USRP hardware is available through email only. If the product arrived in a nonfunctional state or you require technical assistance, please contact [mailto:support@ettus.com support@ettus.com]. Please allow 24 to 48 hours for response by email, depending on holidays and weekends, although we are often able to reply more quickly than that.

We also recommend that you subscribe to the community mailing lists. The mailing lists have a responsive and knowledgeable community of hundreds of developers and technical users who are located around the world. When you join the community, you will be connected to this group of people who can help you learn about SDR and respond to your technical and specific questions. Often your question can be answered quickly on the mailing lists. Each mailing list also provides an archive of all past conversations and discussions going back many years. Your question or problem may have already been addressed before, and a relevant or helpful solution may already exist in the archive.

Discussions involving the USRP hardware and the UHD software itself are best addressed through the '''usrp-users''' mailing list at [http://usrp-users.ettus.com http://usrp-users.ettus.com].

Discussions involving the use of [http://gnuradio.org/ GNU Radio] with USRP hardware and UHD software are best addressed through the '''discuss-gnuradio''' mailing list at [https://lists.gnu.org/mailman/listinfo/discussgnuradio https://lists.gnu.org/mailman/listinfo/discussgnuradio].

Discussions involving the use of [http://openbts.org/ OpenBTS®] with USRP hardware and UHD software are best addressed through the '''openbts-discuss''' mailing list at [https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss].

The support page on our website is located at [https://www.ettus.com/support https://www.ettus.com/support]. The Knowledge Base is located at [https://kb.ettus.com https://kb.ettus.com].

==Legal Considerations==
Every country has laws governing the transmission and reception of radio signals. Users are solely responsible for insuring they use their USRP system in compliance with all applicable laws and regulations. Before attempting to transmit and/or receive on any frequency, we recommend that you determine what licenses may be required and what restrictions may apply.

*NOTE: This USRP product is a piece of test equipment.

==Sales and Ordering Support==
If you have any non-technical questions related to your order, then please contact us by email at [mailto:orders@ettus.com orders@ettus.com], or by phone at +14086106399 (Monday-Friday, 8 AM - 5 PM, Pacific Time). Please be sure to include your order number and the serial number of your USRP.

==Terms and Conditions of Sale==
Terms and conditions of sale can be accessed online at the following link: http://www.ettus.com/legal/terms-and-conditions-of-sale

[[Category:Getting Started Guides]]
[[Category:X4x0]]

X300/X310

2025-03-20T21:49:05Z

DylanCaswell: /* X3xx */

== Device Overview ==
The Ettus Research USRP X310 is a high-performance, scalable software defined radio (SDR) platform for designing and deploying next generation wireless communications systems. The hardware architecture combines two extended-bandwidth daughterboard slots covering DC – 6 GHz with up to 160 MHz of baseband bandwidth, multiple high-speed interface options (PCIe, dual 10 GigE, dual 1 GigE), and a large user-programmable Kintex-7 FPGA in a convenient desktop or rack-mountable half-wide 1U form factor.

== Key Features==
===X300===
{|
|style="vertical-align:top"|
* Xilinx Kintex-7 XC7K325T FPGA
* 14 bit 200 MS/s ADC
* 16 bit 800 MS/s DAC
* Frequency range: DC - 6 GHz with suitable daughterboard
* Up 160MHz bandwidth per channel
* Two wide-bandwidth RF daughterboard slots
* Optional GPSDO
* Multiple high-speed interfaces (Dual 10G, PCIe Express, ExpressCard, Dual 1G)
|[[File:Product x300.jpg|250px|center]]
|}

===X310===
{|
|style="vertical-align:top"|
* Xilinx Kintex-7 XC7K410T FPGA
* 14 bit 200 MS/s ADC
* 16 bit 800 MS/s DAC
* Frequency range: DC - 6 GHz with suitable daughterboard
* Up 160MHz bandwidth per channel
* Two wide-bandwidth RF daughterboard slots
* Optional GPSDO
* Multiple high-speed interfaces (Dual 10G, PCIe Express, ExpressCard, Dual 1G)
|[[File:Product x310.jpg|250px|center]]
|}

==Compatible Daughterboards==
* WBX-120 / WBX-40
* SBX-120 / SBX-40
* CBX-120 / CBX-40
* UBX-160 / UBX-40
* BasicTX / BasicRX
* LFRX / LFTX
* TwinRX
* DBSRX2 (EOL)
* RFX Series (EOL)
* TVRX2 (EOL)

==RF Specifications==
===RF Performance Data (with SBX-120)===
* SSB/LO Suppression -35/50 dBc
* Phase Noise 3.5 GHz 1.0 deg RMS
* Phase Noise 6 GHz 1.5 deg RMS
* Power Output >10dBm
* IIP3 (@ typ NF) 0dBm
* Typical Noise Figure 8dB

==Hardware Specifications==
* Ettus Research recommends to always use the latest stable version of UHD

===X300===
* Current Hardware Revision: 8
* Minimum version of UHD required: 3.9.0

===X310===
* Current Hardware Revision: 8
* Minimum version of UHD required: 3.9.0

===Clocking and Sampling Rates===
There are two master clock rates (MCR) supported on the X300 and X310: 200.0 MHz and 184.32 MHz.

The sampling rate must be an integer decimation rate of the MCR. Ideally, this decimation factor should be an even number. An odd decimation factor will result in additional unwanted attenuation (roll-off from the CIC filter in the DUC and DDC blocks in the FPGA). The valid decimation rates are between 1 and 1024.

For the MCR of 200.0 MHz, the achievable sampling rates using an even decimation factor are 200.0, 100.0, 50.0, 33.33, 25.0, 20.0, 16.67, 14.286 Msps, ... 195.31 Ksps.

For the MCR of 184.32 MHz, the achievable sampling rates using an even decimation factor are 184.32, 92.16, 46.08, 30.72, 23.04, 18.432, 15.36, 13.166 Msps, ... 180.0 Ksps.

If the desired sampling rate is not directly supported by the hardware, then it will be necessary to re-sample in software. This can be done in C++ using libraries such as Liquid DSP [https://github.com/jgaeddert/liquid-dsp], or can be done in GNU Radio, in which there are three blocks that perform sampling rate conversion.

==Physical Specifications==

===Dimensions===
27.7 x 21.8 x 3.9 cm

===Weight===
With 2x SBX-120: 1.7kg

===Drawings===
* [[Media:cu ettus-x3xx.pdf| Enclosure]]
* [[Media:cu x3xx motherboard cca.pdf| Motherboard]]
* [[Media:cu Rackmount Ettus-X3xx.pdf| Rackmount kit]]

===CAD/STP Models===
====X3xx====
* [[Media:cu x3xx motherboard cca.stp.gz| Motherboard Version 1]]

* [https://kb.ettus.com/images/0/03/cu_x3xx_motherboard_cca2.stp Motherboard Version 2, updated March 2025]

====X3xx Enclosure====
* [[Media:cu ettus x3xx.stp.gz|Enclosure]]

==Environmental Specifications==
===Operating Temperature Range===
* X300/X310: 25 °C

===Operating Humidity Range===
* 10% to 90% non-condensing

==Schematics==
===X300/X310===
[http://files.ettus.com/schematics/x300/x3xx.pdf X300/X310 Schematics]

==Key Component Datasheets==
{| class="wikitable" style="width:80%"
!Part Number
!Description
!Schematic ID (Page)
|-

|[http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf XC7K325T] / [http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf XC7K410T]
|FPGA
|U23 (3,5,8,9,10,18)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/AD9146.PDF AD9146]
|Dual Channel, 16-Bit, 1230 MSPS DAC
|U12, U36 (7)
|-

|[http://www.ti.com/lit/ds/slas635b/slas635b.pdf ADS62P48]
|Dual Channel, 14-Bit 210 MSPS ADC
|U11, U35 (6)
|-

|[https://www.fairchildsemi.com/datasheets/FI/FIN1002.pdf FIN1002]
|High Speed Differential Receiver
|U3, U5, U31, U32 (4)
|-

|[http://ww1.microchip.com/downloads/en/DeviceDoc/20001203U.pdf 24LC256T]
|EEPROM
|U530 (11)
|-

|[http://www.ti.com/lit/ds/symlink/lmk04816.pdf LMK04816BISQ/NOPB_1/3]
|Jitter Cleaner With Dual Loop PLLs
|U531 (11)
|-

|[http://www.micrel.com/_PDF/HBW/sy89547l.pdf SY89547LMGTR]
|Multiplexer
|U506 (12)
|-

|[http://www.ti.com/lit/ds/symlink/sn74aup1t17.pdf SN74AUP1T17]
|Single Schmitt-Trigger Buffer Gate
|U6, U519 (12)
|-

|[http://www.ti.com/lit/ds/symlink/tps54620.pdf TPS54620RGYT]
|Synchronous Step Down SWIFT™ Converter
|U515 (21); U516 (26)
|-

|[http://cds.linear.com/docs/en/datasheet/1764fb.pdf LT1764EQ-3.3]
|Voltage Regulator
|U27 (21); U516 (26)
|-

|[http://www.ti.com/lit/ds/symlink/tps7a47.pdf TPS7A47]
|Voltage Regulator
|U28, U532 (21)
|-

|[http://cds.linear.com/docs/en/datasheet/3603fc.pdf LTC3603EUF_TRPBF]
|Monolithic Synchronous Step-Down Regulator
|U517 (23); U500 (25); U514, U513 (27)
|-

|[http://www.ti.com/lit/ds/symlink/tps77625.pdf TPS77625_SM]
|Low-Dropout Voltage Regulators
|U30 (23)
|-

|[http://www.ti.com/lit/ds/symlink/tps79318-ep.pdf TPS79318_SM]
|Low-Dropout Voltage Regulators
|U510 (27)
|-

|[[Media:agile9598503.pdf|OSC-96MHZ-724821-01]]
|Voltage Controlled Crystal Oscillator
|U25 (11)
|-

|}

==GPSDO==
* Support GPSDO NMEA Strings
* [http://www.jackson-labs.com/assets/uploads/main/LC_XO_specsheet.pdf JacksonLabs LC_XO]

===Sensors===
You can query the lock status with the <code>gps_locked</code> sensor, as well as obtain raw NMEA sentences using the <code>gps_gprmc</code>, and <code>gps_gpgga</code> sensors. Location information can be parsed out of the <code>gps_gpgga</code> sensor by using <code>gpsd</code> or another NMEA parser.

==FPGA==
* Utilization statistics are subject to change between UHD releases. This information is current as of UHD 3.9.4 and was taken directly from Xilinx Vivado 2014.4.

===X300===
<pre>
1. Slice Logic
--------------

+----------------------------+-------+-----------+-------+
| Site Type | Used | Available | Util% |
+----------------------------+-------+-----------+-------+
| Slice LUTs | 61622 | 203800 | 30.23 |
| LUT as Logic | 52887 | 203800 | 25.95 |
| LUT as Memory | 8735 | 64000 | 13.64 |
| LUT as Distributed RAM | 1878 | | |
| LUT as Shift Register | 6857 | | |
| Slice Registers | 62961 | 407600 | 15.44 |
| Register as Flip Flop | 62961 | 407600 | 15.44 |
| Register as Latch | 0 | 407600 | 0.00 |
| F7 Muxes | 1209 | 101900 | 1.18 |
| F8 Muxes | 150 | 50950 | 0.29 |
+----------------------------+-------+-----------+-------+

3. Memory
---------

+-------------------+------+-----------+-------+
| Site Type | Used | Available | Util% |
+-------------------+------+-----------+-------+
| Block RAM Tile | 409 | 445 | 91.91 |
| RAMB36/FIFO* | 398 | 445 | 89.43 |
| RAMB36E1 only | 398 | | |
| RAMB18 | 22 | 890 | 2.47 |
| RAMB18E1 only | 22 | | |
+-------------------+------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1

4. DSP
------

+----------------+------+-----------+-------+
| Site Type | Used | Available | Util% |
+----------------+------+-----------+-------+
| DSPs | 123 | 840 | 14.64 |
| DSP48E1 only | 123 | | |
+----------------+------+-----------+-------+

</pre>

===X310===
<pre>
1. Slice Logic
--------------

+----------------------------+-------+-----------+-------+
| Site Type | Used | Available | Util% |
+----------------------------+-------+-----------+-------+
| Slice LUTs | 61616 | 254200 | 24.23 |
| LUT as Logic | 52885 | 254200 | 20.80 |
| LUT as Memory | 8731 | 90600 | 9.63 |
| LUT as Distributed RAM | 1878 | | |
| LUT as Shift Register | 6853 | | |
| Slice Registers | 62958 | 508400 | 12.38 |
| Register as Flip Flop | 62958 | 508400 | 12.38 |
| Register as Latch | 0 | 508400 | 0.00 |
| F7 Muxes | 1209 | 127100 | 0.95 |
| F8 Muxes | 150 | 63550 | 0.23 |
+----------------------------+-------+-----------+-------+

3. Memory
---------

+-------------------+------+-----------+-------+
| Site Type | Used | Available | Util% |
+-------------------+------+-----------+-------+
| Block RAM Tile | 409 | 795 | 51.44 |
| RAMB36/FIFO* | 398 | 795 | 50.06 |
| RAMB36E1 only | 398 | | |
| RAMB18 | 22 | 1590 | 1.38 |
| RAMB18E1 only | 22 | | |
+-------------------+------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1

4. DSP
------

+----------------+------+-----------+-------+
| Site Type | Used | Available | Util% |
+----------------+------+-----------+-------+
| DSPs | 123 | 1540 | 7.98 |
| DSP48E1 only | 123 | | |
+----------------+------+-----------+-------+

</pre>

===FPGA User Modifications===
The Verilog code for the FPGA in the USRP X300 and USRP X310 is open-source, and users are free to modify and customize it for their needs. However, certain modifications may result in either bricking the device, or even in physical damage to the unit. Specifically, changing the I/O interface of the FPGA in any way (do not remove any of the I/O for the PCIe interface, such as <code>x300_pcie_int</code> and <code>LvFpga_Chinch_Interface</code>), or modifying the pin and timing constraint files, could result in physical damage to other components on the motherboard, external to the FPGA, and doing this will void the warranty. Also, even if the PCIe interface is not being used, you cannot remove or reassign these pins in the constraint file. The constraint files should not be modified. Please note that modifications to the FPGA are made at the risk of the user, and may not be covered by the warranty of the device.

==Firmware==

The USRP X300 series runs a small amount of software within the FPGA, within a ZPU soft processor. Its main responsibility is to provide access to some registers, handle the networking stacks, and monitor the USRP status.

The source code for the ZPU is stored in <code>firmware/usrp3/</code> in the UHD repository. To modify the firmware, you need to download a recent ZPU compiler (e.g. from https://github.com/zylin/zpugcc/tree/master/releases/20150428). Unpack the tarball (e.g., into <code>/usr/local</code>) and make sure the <code>zpu-elf-gcc</code> binary is in your path. Then, execute the following steps:
* Create and enter a build directory: <code>mkdir build && cd build</code>
* Run cmake: <code>cmake /path/to/firmware/usrp3/</code>
** If all is correctly configured, and the ZPU compiler can be found, this will pass without errors.
* Build the firmware: <code>make</code>
** This should yield output similar to this:

<pre>
Scanning dependencies of target x300
[ 79%] Generating x300_main.map
[ 83%] Generating x300_main.bin
[ 87%] Generating x300_main.ihx
[ 91%] Generating x300_main.dump
[ 95%] Generating x300_main.rom
[100%] Generating x300_main.coe
[100%] Built target x300
</pre>

* These files will be copied into the <code>build/x310</code> directory.
* To non-persistently load the newly built firmware image into the running FPGA image, simply launch a UHD session with the <code>fw</code> parameter. The binary must be within UHD's image dir, e.g. by copying x300_main.bin to the default image directory (e.g., <code>/usr/local/share/uhd/images</code>) or by temporarily setting the <code>UHD_IMAGES_DIR</code> variable:

UHD_IMAGES_DIR=/path/to/build/x300 uhd_usrp_probe --args type=x300,fw=x300_main.bin

* To permanently bake the firmware image into the FPGA bitfile, copy the file <code>x300_main.coe</code> to <code>fpga/usrp3/top/x300/ip/bootram/bootram.coe</code> and rebuild the bitfile.

==Interfaces and Connectivity==
Follow the links below for additional information on configuring each interface for the USRP X300 or X310 SDRs.

*[http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_10gige Dual 10 Gigabit Ethernet] - 200 MS/s Full Duplex @ 16-bit
*[http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_pcie PCIe Express (Desktop)] - 200 MS/s Full Duplex @ 16-bit
*[http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_pcie_laptop ExpressCard (Laptop)] - 50 MS/s Full Duplex @ 16-bit
*[http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_1gige Dual 1 Gigabit Ethernet] - 25 MS/s Full Duplex @ 16-bit

===Front Panel===
{|
| style="width:50%" |

* '''JTAG''': USB connector for the on-board USB-JTAG programmer
* '''RF A Group'''
** '''TX/RX LED''': Indicates that data is streaming on the TX/RX channel on daughterboard A
** '''RX2 LED''': Indicates that data is streaming on the RX2 channel on daughterboard A
* '''REF''': Indicates that the external Reference Clock is locked
* '''PPS''': Indicates a valid PPS signal by pulsing once per second
* '''AUX I/O''': Front panel GPIO connector.
* '''GPS''': Indicates that GPS reference is locked
* '''LINK''': Indicates that the host computer is communicating with the device (Activity)
* '''RF B Group'''
** '''TX/RX LED''': Indicates that data is streaming on the TX/RX channel on daughterboard B
** '''RX2 LED''': Indicates that data is streaming on the RX2 channel on daughterboard B
* '''PWR''': Power switch

| style="vertical-align:top" | [[File:x3x0 fp overlay.png]]
|}

===Rear Panel===
{|
| style="width:50%" |
* '''PWR''': Connector for the USRP-X Series power supply
* '''1G/10G ETH''': SFP+ ports for Ethernet interfaces
* '''REF OUT''': Output port for the exported reference clock
* '''REF IN''': Reference clock input
* '''PCIe x4''': Connector for Cabled PCI Express link
* '''PPS/TRIG OUT''': Output port for the PPS signal
* '''PPS/TRIG IN''': Input port for the PPS signal
* '''GPS''': Connection for the GPS antenna

| style="vertical-align:top" | [[File:x3x0 rp overlay.png]]
|}

===Ref Clock - 10 MHz===

An external 10 MHz reference clock may be used. The optimal signal is a square wave as created by the [https://kb.ettus.com/OctoClock_CDA-2990 OctoClock/CDDA-2990]. The input signal power level of the reference clock must not exceed +15 dBm.

===PPS - Pulse Per Second===
Using a PPS signal for timestamp synchronization requires a square wave signal with the following a 5Vpp amplitude.

To test the PPS input, you can use the following tool from the UHD examples:

* <code><args></code> are device address arguments (optional if only one USRP device is on your machine)

cd <install-path>/lib/uhd/examples ./test_pps_input –args=<args>

===Front Panel GPIO===
{|
| style="width:50%" |
The GPIO port is not meant to drive big loads. You should not try to source more than 5mA per pin.

The +3.3V is for ESD clamping purposes only and not designed to deliver high currents.

The switching speed is below 10 MHz.

| style="vertical-align:top" | [[File:x3x0 gpio conn.png]]
|}

====Power on state====
The hardware power on state and UHD initial state for the front-panel GPIOs is high-Z. For the X3xx, there are no external pull-ups/pull-downs for the GPIO pins, but the FPGAs do have them and they are configured as follows: X3xx: pull-down.

====Pin Mapping====
* Pin 1: +3.3V
* Pin 2: Data[0]
* Pin 3: Data[1]
* Pin 4: Data[2]
* Pin 5: Data[3]
* Pin 6: Data[4]
* Pin 7: Data[5]
* Pin 8: Data[6]
* Pin 9: Data[7]
* Pin 10: Data[8]
* Pin 11: Data[9]
* Pin 12: Data[10]
* Pin 13: Data[11]
* Pin 14: 0V
* Pin 15: 0V

'''Note''': Please see the [http://files.ettus.com/manual/page_gpio_api.html E3x0/X3x0 GPIO API] for information on configuring and using the GPIO bus.

===On-Board LEDs===
{| class="wikitable"

!LED
!Detail
!Description
|-

| DS1
| 1.2V
| Power
|-

| DS2
| TXRX1
| Red: TX, Green: RX
|-

| DS3
| RX1
| Green: RX
|-

| DS4
| REF
| Reference Lock
|-

| DS5
| PPS
| Flashes on Edge
|-

| DS6
| GPS
| GPS Lock
|-

| DS7
| SFP0
| Link, Right, Green
|-

| DS8
| SFP0
| Link Activity, Left, Yellow
|-

| DS10
| TXRX2
| Red: TX Green: RX
|-

| DS11
| RX2
| Green: RX
|-

| DS12
| 6V
| Daughterboard Power
|-

| DS13
| 3.8V
| Power
|-

| DS14
| 3.3V
| Management Power
|-

| DS15
| 3.3V
| Auxiliary Management Power
|-

| DS16
| 3.3V
| FPGA Power
|-

| DS19
| SFP1
| Link Active, Left, Yellow
|-

| DS20
| SFP1
| Link, Right, Green
|-

| DS21
| LINK
| Link Activity
|-

|}

===Power Connector===
Model: PDP-40 by CUI Inc.

Power plug connectors for custom power harnesses can be purchased here: https://www.digikey.com/products/en?KeyWords=CP-7340-ND&WT.z_cid=sp_102_buynow

Assembly instructions: [[Media:pdp-40.pdf]]

====Pin Detail====
* Pins #1 / #2: 12v
* Pins #3 / #4: Ground

[[File:pdp 40 power detail.png]]

==Certifications==
===RoHS===
As of December 1st, 2010 all Ettus Research products are RoHS compliant unless otherwise noted. More information can be found at [http://ettus.com/legal/rohs-information http://ettus.com/legal/rohs-information]

===China RoHS===
'''Management Methods for Controlling Pollution Caused by Electronic Information Products Regulation'''

'''Chinese Customers'''

National Instruments is in compliance with the Chinese policy on the Restriction of Hazardous Substances (RoHS) used in Electronic Information Products. For more information about the National Instruments China RoHS compliance, visit [http://www.ni.com/environment/rohs_china ni.com/environment/rohs_china].

==Certificate of Volatility==

Found on the [https://www.ni.com/en/support/documentation/product-certifications.html NI Product Certifications lookup tool] [https://www.ni.com/pdf/manuals/377356a.pdf here].

==Downloads==
[http://files.ettus.com/manual/md_fpga.html FPGA Resources]

[http://files.ettus.com/binaries/uhd_stable/ UHD Stable Binaries]

[https://github.com/EttusResearch/uhd UHD Source Code on Github]

==Choosing USRP X310 vs USRP X300==
In terms of host bandwidth, interface options, and all other hardware features the USRP X300 and USRP 310 are identical. However, the USRP X310 provides a larger FPGA, a Xilinx XC7K410T, as opposed to XC7K325T. While both options provide a significant amount of free resources for custom FPGA development, the XC7K410T provides additional design margin, which translates to ease of development and future expandability. Most users choose the USRP X310 for their development.

{| class="wikitable" style="margin: auto;"
!colspan="3"|USRP X300 and X310 FPGA Resource Summary
|-
|rowspan="2"|Resource Type
|USRP X300 (XC7K325T)
|USRP X310 (XC7K410T)
|-
|Count
|Count
|-
|DSP48 Blocks
|840
|1540
|-
|Block Rams (18kB)
|890
|1590
|-
|Logic Cells
|326,080
|406,720
|-
|Slices (logic)
|50,950
|63,550
|-
|}

For up-to-date information on FPGA resource utilization in the stock FPGA design, please see "USRP 300/X310 FPGA Resources" in the Ettus Research knowledge base (https://kb.ettus.com).

==Choosing an RF Daughterboard==
With the increased sample rates used by the USRP X300 and USRP X310, these new device can support extended-bandwidth daughterboards. The WBX-120, SBX-120, and CBX-120 are recommended to take advantage of the full bandwidth capability of the USRP X300 and X310. The WBX-120, SBX-120, and CBX-120 have been upgraded from their predecessors (40 MHz) to use 120 MHz baseband filters. You can select your daughterboard based on the center frequency of your primary application.

{| class="wikitable" style="margin: auto;"
!Daughterboard
!Frequency Range
!Bandwidth
|-

|WBX-120
|50 MHz - 2200 MHz
|120 MHz
|-

|SBX-120
|400 MHz - 4400 MHz
|120 MHz
|-

|CBX-120
|1200 MHz - 6000 MHz
|120 MHz
|-

|UBX-160
|10 MHz - 6000 MHz
|160 MHz
|-

|TwinRX
|10 MHz - 6000 MHz
|80 MHz per channel, 160 MHz total
|-

|}

If your application is in the HF frequency range, the LFRX and LFTX are recommended for up to 30 MHz of bandwidth per channel. The BasicRX and BasicTX are ideal for configurations that use an external frontend for tuning and filtering with either an IF or baseband interface.

The USRP X300 and X310 are backward compatible with legacy daughterboards except for the RFX Series and XCVR2450. Please note, while there are two daughterboard slots, the USRP X300/X310 can only support a single TVRX2.

If you plan to transmit or receive over the air, you should also purchase an antenna.

==Choosing a Host Interface==

The USRP X300/X310 provide three interface options – 1 Gigabit Ethernet (1 GigE), 10 Gigabit Ethernet (10 GigE), and PCI-Express (PCIe). The PCIe interface is always available regardless of what FPGA image is loaded. Ettus ships two FPGA image variants, the HG or HGS image which has one 1 GigE interfaces and one 10 GigE interfaces, and the XG image which has two 10 GigE interfaces. Generally, Ettus Research recommends using 10 GigE to achieve the maximum throughput available from the USRP X300/X310. PCIe is recommended for applications that require the lowest possible latency, which is a desirable characteristic for PHY/MAC research. If your application does not require the full bandwidth of the USRP ™ X300 and X310, the 1 GigE interface serves as a cost-effective fall-back option. Ettus Research provides a complete interface kit for each of these options, which is also shown in Table 3.

{| class="wikitable" style="margin: auto;"
!colspan="4"|Table 3 - Interface Performance Summary
|-
!Interface
!Throughput (MS/s @ 16-bit)
!Target
!Recommended Kit
|-
|1 Gigabit
|25 MS/s
|Desktop/Laptop
|Components provided with USRP X300/X310 kit.
For additional connections, purchase the following:
[https://www.ettus.com/product/details/1GIGE-KIT SFP Adapter + GigE Cable]
|-
|10 Gigabit
|200 MS/s
|Desktop
|[https://www.ettus.com/product/details/10GIGE-KIT 10 GigE Interface Kit]
|-
|PCI-Express
(PCIe, 4 lane)
|200 MS/S
|Desktop
|[https://www.ettus.com/product/details/PCIE-KIT PCI-Express Desktop Kit]
|-
|Express Card
(PCIe, 1 lane)
|50 MS/s
|Laptop
|[https://www.ettus.com/product/details/ECARD-KIT ExpressCard Kit]
|-
|}

[[File:Connectivity 2.png|700px|center]]

<center>Figure 2 - Host Interface Options</center>

===10 Gigabit Ethernet===
See [https://kb.ettus.com/Using_Dual_10_Gigabit_Ethernet_on_the_USRP_X300/X310 this app note] for how to use the X3x0 with dual 10 GbE links.

'''Recommended 10 Gigabit Ethernet Cards'''
* Intel X520-DA2
** [http://ark.intel.com/products/39776/Intel-Ethernet-Converged-Network-Adapter-X520-DA2 Intel® Ethernet Converged Network Adapter X520-DA2]
* Intel X520-DA1
** [http://ark.intel.com/products/68669/Intel-Ethernet-Converged-Network-Adapter-X520-DA1 Intel® Ethernet Converged Network Adapter X520-DA1 ]
* Intel X710-DA2
** [http://ark.intel.com/products/83964/Intel-Ethernet-Converged-Network-Adapter-X710-DA2 Intel® Ethernet Converged Network Adapter X710-DA2 ]
* Intel X710-DA4
** [http://ark.intel.com/products/83965/Intel-Ethernet-Converged-Network-Adapter-X710-DA4 Intel® Ethernet Converged Network Adapter X710-DA4 ]
* Mellanox MCX4121A-ACAT
** [https://store.mellanox.com/products/mellanox-mcx4121a-acat-connectx-4-lx-en-network-interface-card-25gbe-dual-port-sfp28-pcie3-0-x8-rohs-r6.html Mellanox MCX4121A-ACAT ]

==International Power Supply Options==
The power supply provided with the USRP X300/X310 kit is packaged with a power cord that is compatible with power outlets in the US/Japan. If you are not using the USRP X300/X310 in the US/Japan, we recommend purchasing the International USRP X300/X310 Power Cord set.

==Option: GPS Disciplined, Oven-Controlled Oscillator (GPSDO)==
The USRP X300 and USRP X310 provide the option to integrate a high-accuracy GPS-disciplined oscillator (GPSDO). The GPSDO improves the accuracy of the internal frequency reference to 20 ppb, or 0.1 ppb if the GPS is synchronized to the GPS constellation. When synchronized to the GPS constellation, all USRP ™ devices will also be synchronized in time within 50 ns.

{| class="wikitable" style="margin: auto;"
|
!Internal TCXO
!GPS-Disciplined Clock
|-
|Frequency Reference
|TCXO
|OCXO
|-
|Frequency Accuracy (unlocked)
|± 2.5ppm
± 2,500 Hz @ 1 GHz
|± 25 ppb
± 25 Hz @ 1 GHz
|-
|Frequency Accuracy
|
|± 0.01ppb
|-
|(GPS-Disciplined)
|
|~ ± 0.01 Hz @ 1 GHz
|-
|GPS Time Sync Accuracy
|
|±50ns to UTC Time**
|-
|10 MHz Reference Phase Drift with GPS Sync
|
|<±20ns After 1 Hour**
|-
|}

==Option: Antenna Kit for GPSDO==
The GPSDO Mini Kit will improve the accuracy of the USRP reference clock, even if it does not receive signals from the GPS Constellation. However, to achieve the best accuracy possible, and to achieve global timing alignment across multiple USRPs, Ettus Research recommends the GPSDO Mini Antenna Kit.

==Option: General Purpose Input/Output (GPIO) Kit==
The USRP X300 and X310 include a DB15 connector on the front panel that provides convenient access to GPIO signals. Each pin can be configured as an input or output, uses 3.3V-level logic, and is protected with basic anti-static circuitry. These pins can be used to control external devices like RF switches and amplifiers, trigger software events on the host, or even provide basic debugging functionality. The USRP GPIO Kit is an affordable option that provides access to these signals with a DB15 cable and a breakout board. The breakout board allows the user to connect external devices through a terminal block. The user can also solder wires and components into the dedicated prototyping area.

==Option: Cables for MIMO Expansion==
Multiple USRP X300/X310s can be synchronized for coherent operation by sharing a common 10 MHz and 1 PPS signal. We recommend using a star-distribution topology with an OctoClock or OctoClock-G, as seen in Figure 4. This requires matched length cables to be used for both 10 MHz and 1 PPS.

For more information about MIMO operation, please see the MIMO and Synchronization Application Note.
[[File:8mimo.png|700px|center]]
<center>Figure 4 - Star-Distribution of 10 MHz/PPS Signals with OctoClock</center>

==Option: USRP X300/X310 Rackmount==

The USRP X300 and X310 were designed to be used with a [https://www.ettus.com/all-products/rackmount-1u/ 1U Rackmount Assembly] for building high-density MIMO systems in a compact and well-organized setup. This mount supports one or two compatible USRPs, and if two are mounted then there are rubber standoffs between the USRPs to avoid both direct contact and surface scratching. If the user will be developing in a laboratory environment or building a high-channel count USRP system, then a 1U Rackmount Assembly is highly recommended. This specific mount is compatible with only the USRP X300 and X310, and allows the integration of up to four bidirectional -- or eight receive-only -- RF channels per 1U.

==Guidance on SFP+ Adapters for Fiber Connectivity on USRP X300/X310==

Ettus Research currently offers direct-connect, copper cabling accessories for the USRP X300 and USRP X310. However, it is also possible to use multi-mode fiber instead of copper connections for these devices.

The USRP X Series is compatible with most brands of SFP+ fiber adapters. In some cases, other equipment in the systems such as 1/10 Gigabith Ethernet switches are only compatible with specific brands of SFP+ adapters and cables. As a general rule, we recommend checking compatibility with the switches and network cards in your system before purchasing an adapter.

Ettus Research does test the USRP X Series devices with our [https://www.ettus.com/product/details/10GIGE-KIT 10 Gigabit Ethernet Connectivity Kit] and a Blade Networks G8124 1/10 GigE switch. Here are is a list of known-good cables and adapters.

Ettus Research has only tested multi-mode fiber accessories.

===Known-Good Adapters===
* [https://approvedoptics.com/blade-networks-bn-ckm-sp-sr/ Approved Optics Blade Networks BN-CKM-SP-SR-A]

===Known-Good Cables===
* [https://www.colfaxdirect.com/store/pc/viewPrd.asp?idproduct=995&idcategory=2 Myricom Fiber Cables for 10GBase-SR, 3 Meters 10G-SR-3M]

==Guidance on 10Gb SFP+ to RJ45 Adapters==

Many new motherboards come equipped with an onboard 10Gb RJ45 NIC. It is possible to use a SFP+ to RJ45 adapter and operate at 10Gb speeds using a Cat6/7 Ethernet cables.

Ettus Research has tested the adapters linked below.

===Known-Good Adapters===
* [https://www.amazon.com/10Gtek-SFP-10G-T-S-Compatible-10GBase-T-Transceiver/dp/B01KFBFL16/ 10Gtek SFP+ to RJ45 Copper Module]
* [https://www.prolabs.com/products/transceivers/brocade/sfpplus/100-1000-10000base/10g-sfpp-t-c ProLabs 10G-SFPP-T-C]

==FAQ==
USRP™ X300 and USRP™ X310 SDRs Frequently Asked Questions

* '''What is the bandwidth of the USRP X300/X310'''

The ADC rate on each analog RX channel is 200 MS/s quadrature, which provides a theoretical analog bandwidth of approximately 80% of the Nyquist bandwidth of +/- 100 MHz (+/- 80 MHz around the center frequency). The resulting maximum theoretical analog bandwidth is 160 MHz. The actual analog bandwidth may be reduced due the RF daughterboard selected.

RF Daughterboard Bandwidths: See the daughterboard specifications [link]

FPGA Processing Bandwidth: Up to 200 MS/s quadrature.

Host Bandwidth: Up to 200 MS/s quadrature, dependent on selected interface

For more information about achieving the maximum bandwidth with a USRP X300/X310, please see the "USRP X300/X310 Configuration Guide" or the "USRP System Bandwidth" application note.

* '''How can I program the USRP X300/X310'''

Like all other USRP models, the USRP X300 and X310 are compatible with the USRP Hardware Driver™ (UHD) architecture. The UHD architecture is a common driver that allows users to develop and execute applications on a host-PC. UHD provides a direct C++ API to control and stream to/from the USRP X300/X310. It also provides compatibility with a variety of third-party software frameworks including GNU Radio, LabVIEW, and Matlab. You may also customize the FPGA image provided with UHD to integrate your own signal processing. For more information about UHD, and supported software frameworks, please see:

http://files.ettus.com/manual/

* '''How do I update the FPGA images and firmware with the latest from UHD'''

You can find more information about updating the FPGA image in the UHD manual: https://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_getting_started_fpga_update

* '''How can I modify the FPGA of the USRP X300/X310'''

The source code (Verilog) for the USRP X300/X310 is available in the UHD repository. The build process leverages the existing CMAKE build system used to compile the host-side driver. A Linux-based setup will provide the best results.

Which FPGA toolchain required to build the FPGA images will depend upon your version of UHD. For more details please see the [[UHD]] Software Resource page.

* '''How much free space is available in the USRP X300/X310 FPGA'''

Please see the USRP X300/X310 FPGA resources page for more information.

* '''What type of PC setup is recommended for use with the USRP X300/X310'''

The type of PC required depends heavily on the complexity and bandwidth of the application. To demonstrate the USRP X300/X310, we typically use a desktop computer with a quadcore i7, 8+ GB of DDR3, and install the PCIe interface card that is also provide with the 10 GigE, PCIe, and ExpressCard interface kits.

* '''What frequency range does the USRP X300/X310 cover'''

The frequency range depends on the daughterboard select by the users. For more information, please see the USRP X300/X310 Configuration Guide.

* '''What components do I need to purchase for a complete USRP X300/X310 system'''

For a more comprehensive guide, please see the USRP X300/X310 Configuration Guide.

* '''What is the difference between the USRP X300/X310'''

The USRP X310 includes a larger Kintex-7 series FPGA (XC7K410T) with additional development resources for more complex designs. The USRP X300 includes the smaller XC7K325T FPGA.

* '''What is the part number of the X300/X310 power connector'''
Model: PDP-40 by CUI Inc.
Power plug connectors for custom power harnesses can be purchased here: https://www.digikey.com/products/en?KeyWords=CP-7340-ND&WT.z_cid=sp_102_buynow

[[Category:Hardware Resources]]

X300/X310

2025-03-20T21:47:50Z

DylanCaswell: /* X3xx */

== Device Overview ==
The Ettus Research USRP X310 is a high-performance, scalable software defined radio (SDR) platform for designing and deploying next generation wireless communications systems. The hardware architecture combines two extended-bandwidth daughterboard slots covering DC – 6 GHz with up to 160 MHz of baseband bandwidth, multiple high-speed interface options (PCIe, dual 10 GigE, dual 1 GigE), and a large user-programmable Kintex-7 FPGA in a convenient desktop or rack-mountable half-wide 1U form factor.

== Key Features==
===X300===
{|
|style="vertical-align:top"|
* Xilinx Kintex-7 XC7K325T FPGA
* 14 bit 200 MS/s ADC
* 16 bit 800 MS/s DAC
* Frequency range: DC - 6 GHz with suitable daughterboard
* Up 160MHz bandwidth per channel
* Two wide-bandwidth RF daughterboard slots
* Optional GPSDO
* Multiple high-speed interfaces (Dual 10G, PCIe Express, ExpressCard, Dual 1G)
|[[File:Product x300.jpg|250px|center]]
|}

===X310===
{|
|style="vertical-align:top"|
* Xilinx Kintex-7 XC7K410T FPGA
* 14 bit 200 MS/s ADC
* 16 bit 800 MS/s DAC
* Frequency range: DC - 6 GHz with suitable daughterboard
* Up 160MHz bandwidth per channel
* Two wide-bandwidth RF daughterboard slots
* Optional GPSDO
* Multiple high-speed interfaces (Dual 10G, PCIe Express, ExpressCard, Dual 1G)
|[[File:Product x310.jpg|250px|center]]
|}

==Compatible Daughterboards==
* WBX-120 / WBX-40
* SBX-120 / SBX-40
* CBX-120 / CBX-40
* UBX-160 / UBX-40
* BasicTX / BasicRX
* LFRX / LFTX
* TwinRX
* DBSRX2 (EOL)
* RFX Series (EOL)
* TVRX2 (EOL)

==RF Specifications==
===RF Performance Data (with SBX-120)===
* SSB/LO Suppression -35/50 dBc
* Phase Noise 3.5 GHz 1.0 deg RMS
* Phase Noise 6 GHz 1.5 deg RMS
* Power Output >10dBm
* IIP3 (@ typ NF) 0dBm
* Typical Noise Figure 8dB

==Hardware Specifications==
* Ettus Research recommends to always use the latest stable version of UHD

===X300===
* Current Hardware Revision: 8
* Minimum version of UHD required: 3.9.0

===X310===
* Current Hardware Revision: 8
* Minimum version of UHD required: 3.9.0

===Clocking and Sampling Rates===
There are two master clock rates (MCR) supported on the X300 and X310: 200.0 MHz and 184.32 MHz.

The sampling rate must be an integer decimation rate of the MCR. Ideally, this decimation factor should be an even number. An odd decimation factor will result in additional unwanted attenuation (roll-off from the CIC filter in the DUC and DDC blocks in the FPGA). The valid decimation rates are between 1 and 1024.

For the MCR of 200.0 MHz, the achievable sampling rates using an even decimation factor are 200.0, 100.0, 50.0, 33.33, 25.0, 20.0, 16.67, 14.286 Msps, ... 195.31 Ksps.

For the MCR of 184.32 MHz, the achievable sampling rates using an even decimation factor are 184.32, 92.16, 46.08, 30.72, 23.04, 18.432, 15.36, 13.166 Msps, ... 180.0 Ksps.

If the desired sampling rate is not directly supported by the hardware, then it will be necessary to re-sample in software. This can be done in C++ using libraries such as Liquid DSP [https://github.com/jgaeddert/liquid-dsp], or can be done in GNU Radio, in which there are three blocks that perform sampling rate conversion.

==Physical Specifications==

===Dimensions===
27.7 x 21.8 x 3.9 cm

===Weight===
With 2x SBX-120: 1.7kg

===Drawings===
* [[Media:cu ettus-x3xx.pdf| Enclosure]]
* [[Media:cu x3xx motherboard cca.pdf| Motherboard]]
* [[Media:cu Rackmount Ettus-X3xx.pdf| Rackmount kit]]

===CAD/STP Models===
====X3xx====
* [[Media:cu x3xx motherboard cca.stp.gz| Motherboard Version 1]]

* [[Media:cu x3xx motherboard cca2.stp| Motherboard Version 2, updated March 2025]]

====X3xx Enclosure====
* [[Media:cu ettus x3xx.stp.gz|Enclosure]]

==Environmental Specifications==
===Operating Temperature Range===
* X300/X310: 25 °C

===Operating Humidity Range===
* 10% to 90% non-condensing

==Schematics==
===X300/X310===
[http://files.ettus.com/schematics/x300/x3xx.pdf X300/X310 Schematics]

==Key Component Datasheets==
{| class="wikitable" style="width:80%"
!Part Number
!Description
!Schematic ID (Page)
|-

|[http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf XC7K325T] / [http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf XC7K410T]
|FPGA
|U23 (3,5,8,9,10,18)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/AD9146.PDF AD9146]
|Dual Channel, 16-Bit, 1230 MSPS DAC
|U12, U36 (7)
|-

|[http://www.ti.com/lit/ds/slas635b/slas635b.pdf ADS62P48]
|Dual Channel, 14-Bit 210 MSPS ADC
|U11, U35 (6)
|-

|[https://www.fairchildsemi.com/datasheets/FI/FIN1002.pdf FIN1002]
|High Speed Differential Receiver
|U3, U5, U31, U32 (4)
|-

|[http://ww1.microchip.com/downloads/en/DeviceDoc/20001203U.pdf 24LC256T]
|EEPROM
|U530 (11)
|-

|[http://www.ti.com/lit/ds/symlink/lmk04816.pdf LMK04816BISQ/NOPB_1/3]
|Jitter Cleaner With Dual Loop PLLs
|U531 (11)
|-

|[http://www.micrel.com/_PDF/HBW/sy89547l.pdf SY89547LMGTR]
|Multiplexer
|U506 (12)
|-

|[http://www.ti.com/lit/ds/symlink/sn74aup1t17.pdf SN74AUP1T17]
|Single Schmitt-Trigger Buffer Gate
|U6, U519 (12)
|-

|[http://www.ti.com/lit/ds/symlink/tps54620.pdf TPS54620RGYT]
|Synchronous Step Down SWIFT™ Converter
|U515 (21); U516 (26)
|-

|[http://cds.linear.com/docs/en/datasheet/1764fb.pdf LT1764EQ-3.3]
|Voltage Regulator
|U27 (21); U516 (26)
|-

|[http://www.ti.com/lit/ds/symlink/tps7a47.pdf TPS7A47]
|Voltage Regulator
|U28, U532 (21)
|-

|[http://cds.linear.com/docs/en/datasheet/3603fc.pdf LTC3603EUF_TRPBF]
|Monolithic Synchronous Step-Down Regulator
|U517 (23); U500 (25); U514, U513 (27)
|-

|[http://www.ti.com/lit/ds/symlink/tps77625.pdf TPS77625_SM]
|Low-Dropout Voltage Regulators
|U30 (23)
|-

|[http://www.ti.com/lit/ds/symlink/tps79318-ep.pdf TPS79318_SM]
|Low-Dropout Voltage Regulators
|U510 (27)
|-

|[[Media:agile9598503.pdf|OSC-96MHZ-724821-01]]
|Voltage Controlled Crystal Oscillator
|U25 (11)
|-

|}

==GPSDO==
* Support GPSDO NMEA Strings
* [http://www.jackson-labs.com/assets/uploads/main/LC_XO_specsheet.pdf JacksonLabs LC_XO]

===Sensors===
You can query the lock status with the <code>gps_locked</code> sensor, as well as obtain raw NMEA sentences using the <code>gps_gprmc</code>, and <code>gps_gpgga</code> sensors. Location information can be parsed out of the <code>gps_gpgga</code> sensor by using <code>gpsd</code> or another NMEA parser.

==FPGA==
* Utilization statistics are subject to change between UHD releases. This information is current as of UHD 3.9.4 and was taken directly from Xilinx Vivado 2014.4.

===X300===
<pre>
1. Slice Logic
--------------

+----------------------------+-------+-----------+-------+
| Site Type | Used | Available | Util% |
+----------------------------+-------+-----------+-------+
| Slice LUTs | 61622 | 203800 | 30.23 |
| LUT as Logic | 52887 | 203800 | 25.95 |
| LUT as Memory | 8735 | 64000 | 13.64 |
| LUT as Distributed RAM | 1878 | | |
| LUT as Shift Register | 6857 | | |
| Slice Registers | 62961 | 407600 | 15.44 |
| Register as Flip Flop | 62961 | 407600 | 15.44 |
| Register as Latch | 0 | 407600 | 0.00 |
| F7 Muxes | 1209 | 101900 | 1.18 |
| F8 Muxes | 150 | 50950 | 0.29 |
+----------------------------+-------+-----------+-------+

3. Memory
---------

+-------------------+------+-----------+-------+
| Site Type | Used | Available | Util% |
+-------------------+------+-----------+-------+
| Block RAM Tile | 409 | 445 | 91.91 |
| RAMB36/FIFO* | 398 | 445 | 89.43 |
| RAMB36E1 only | 398 | | |
| RAMB18 | 22 | 890 | 2.47 |
| RAMB18E1 only | 22 | | |
+-------------------+------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1

4. DSP
------

+----------------+------+-----------+-------+
| Site Type | Used | Available | Util% |
+----------------+------+-----------+-------+
| DSPs | 123 | 840 | 14.64 |
| DSP48E1 only | 123 | | |
+----------------+------+-----------+-------+

</pre>

===X310===
<pre>
1. Slice Logic
--------------

+----------------------------+-------+-----------+-------+
| Site Type | Used | Available | Util% |
+----------------------------+-------+-----------+-------+
| Slice LUTs | 61616 | 254200 | 24.23 |
| LUT as Logic | 52885 | 254200 | 20.80 |
| LUT as Memory | 8731 | 90600 | 9.63 |
| LUT as Distributed RAM | 1878 | | |
| LUT as Shift Register | 6853 | | |
| Slice Registers | 62958 | 508400 | 12.38 |
| Register as Flip Flop | 62958 | 508400 | 12.38 |
| Register as Latch | 0 | 508400 | 0.00 |
| F7 Muxes | 1209 | 127100 | 0.95 |
| F8 Muxes | 150 | 63550 | 0.23 |
+----------------------------+-------+-----------+-------+

3. Memory
---------

+-------------------+------+-----------+-------+
| Site Type | Used | Available | Util% |
+-------------------+------+-----------+-------+
| Block RAM Tile | 409 | 795 | 51.44 |
| RAMB36/FIFO* | 398 | 795 | 50.06 |
| RAMB36E1 only | 398 | | |
| RAMB18 | 22 | 1590 | 1.38 |
| RAMB18E1 only | 22 | | |
+-------------------+------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1

4. DSP
------

+----------------+------+-----------+-------+
| Site Type | Used | Available | Util% |
+----------------+------+-----------+-------+
| DSPs | 123 | 1540 | 7.98 |
| DSP48E1 only | 123 | | |
+----------------+------+-----------+-------+

</pre>

===FPGA User Modifications===
The Verilog code for the FPGA in the USRP X300 and USRP X310 is open-source, and users are free to modify and customize it for their needs. However, certain modifications may result in either bricking the device, or even in physical damage to the unit. Specifically, changing the I/O interface of the FPGA in any way (do not remove any of the I/O for the PCIe interface, such as <code>x300_pcie_int</code> and <code>LvFpga_Chinch_Interface</code>), or modifying the pin and timing constraint files, could result in physical damage to other components on the motherboard, external to the FPGA, and doing this will void the warranty. Also, even if the PCIe interface is not being used, you cannot remove or reassign these pins in the constraint file. The constraint files should not be modified. Please note that modifications to the FPGA are made at the risk of the user, and may not be covered by the warranty of the device.

==Firmware==

The USRP X300 series runs a small amount of software within the FPGA, within a ZPU soft processor. Its main responsibility is to provide access to some registers, handle the networking stacks, and monitor the USRP status.

The source code for the ZPU is stored in <code>firmware/usrp3/</code> in the UHD repository. To modify the firmware, you need to download a recent ZPU compiler (e.g. from https://github.com/zylin/zpugcc/tree/master/releases/20150428). Unpack the tarball (e.g., into <code>/usr/local</code>) and make sure the <code>zpu-elf-gcc</code> binary is in your path. Then, execute the following steps:
* Create and enter a build directory: <code>mkdir build && cd build</code>
* Run cmake: <code>cmake /path/to/firmware/usrp3/</code>
** If all is correctly configured, and the ZPU compiler can be found, this will pass without errors.
* Build the firmware: <code>make</code>
** This should yield output similar to this:

<pre>
Scanning dependencies of target x300
[ 79%] Generating x300_main.map
[ 83%] Generating x300_main.bin
[ 87%] Generating x300_main.ihx
[ 91%] Generating x300_main.dump
[ 95%] Generating x300_main.rom
[100%] Generating x300_main.coe
[100%] Built target x300
</pre>

* These files will be copied into the <code>build/x310</code> directory.
* To non-persistently load the newly built firmware image into the running FPGA image, simply launch a UHD session with the <code>fw</code> parameter. The binary must be within UHD's image dir, e.g. by copying x300_main.bin to the default image directory (e.g., <code>/usr/local/share/uhd/images</code>) or by temporarily setting the <code>UHD_IMAGES_DIR</code> variable:

UHD_IMAGES_DIR=/path/to/build/x300 uhd_usrp_probe --args type=x300,fw=x300_main.bin

* To permanently bake the firmware image into the FPGA bitfile, copy the file <code>x300_main.coe</code> to <code>fpga/usrp3/top/x300/ip/bootram/bootram.coe</code> and rebuild the bitfile.

==Interfaces and Connectivity==
Follow the links below for additional information on configuring each interface for the USRP X300 or X310 SDRs.

*[http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_10gige Dual 10 Gigabit Ethernet] - 200 MS/s Full Duplex @ 16-bit
*[http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_pcie PCIe Express (Desktop)] - 200 MS/s Full Duplex @ 16-bit
*[http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_pcie_laptop ExpressCard (Laptop)] - 50 MS/s Full Duplex @ 16-bit
*[http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_1gige Dual 1 Gigabit Ethernet] - 25 MS/s Full Duplex @ 16-bit

===Front Panel===
{|
| style="width:50%" |

* '''JTAG''': USB connector for the on-board USB-JTAG programmer
* '''RF A Group'''
** '''TX/RX LED''': Indicates that data is streaming on the TX/RX channel on daughterboard A
** '''RX2 LED''': Indicates that data is streaming on the RX2 channel on daughterboard A
* '''REF''': Indicates that the external Reference Clock is locked
* '''PPS''': Indicates a valid PPS signal by pulsing once per second
* '''AUX I/O''': Front panel GPIO connector.
* '''GPS''': Indicates that GPS reference is locked
* '''LINK''': Indicates that the host computer is communicating with the device (Activity)
* '''RF B Group'''
** '''TX/RX LED''': Indicates that data is streaming on the TX/RX channel on daughterboard B
** '''RX2 LED''': Indicates that data is streaming on the RX2 channel on daughterboard B
* '''PWR''': Power switch

| style="vertical-align:top" | [[File:x3x0 fp overlay.png]]
|}

===Rear Panel===
{|
| style="width:50%" |
* '''PWR''': Connector for the USRP-X Series power supply
* '''1G/10G ETH''': SFP+ ports for Ethernet interfaces
* '''REF OUT''': Output port for the exported reference clock
* '''REF IN''': Reference clock input
* '''PCIe x4''': Connector for Cabled PCI Express link
* '''PPS/TRIG OUT''': Output port for the PPS signal
* '''PPS/TRIG IN''': Input port for the PPS signal
* '''GPS''': Connection for the GPS antenna

| style="vertical-align:top" | [[File:x3x0 rp overlay.png]]
|}

===Ref Clock - 10 MHz===

An external 10 MHz reference clock may be used. The optimal signal is a square wave as created by the [https://kb.ettus.com/OctoClock_CDA-2990 OctoClock/CDDA-2990]. The input signal power level of the reference clock must not exceed +15 dBm.

===PPS - Pulse Per Second===
Using a PPS signal for timestamp synchronization requires a square wave signal with the following a 5Vpp amplitude.

To test the PPS input, you can use the following tool from the UHD examples:

* <code><args></code> are device address arguments (optional if only one USRP device is on your machine)

cd <install-path>/lib/uhd/examples ./test_pps_input –args=<args>

===Front Panel GPIO===
{|
| style="width:50%" |
The GPIO port is not meant to drive big loads. You should not try to source more than 5mA per pin.

The +3.3V is for ESD clamping purposes only and not designed to deliver high currents.

The switching speed is below 10 MHz.

| style="vertical-align:top" | [[File:x3x0 gpio conn.png]]
|}

====Power on state====
The hardware power on state and UHD initial state for the front-panel GPIOs is high-Z. For the X3xx, there are no external pull-ups/pull-downs for the GPIO pins, but the FPGAs do have them and they are configured as follows: X3xx: pull-down.

====Pin Mapping====
* Pin 1: +3.3V
* Pin 2: Data[0]
* Pin 3: Data[1]
* Pin 4: Data[2]
* Pin 5: Data[3]
* Pin 6: Data[4]
* Pin 7: Data[5]
* Pin 8: Data[6]
* Pin 9: Data[7]
* Pin 10: Data[8]
* Pin 11: Data[9]
* Pin 12: Data[10]
* Pin 13: Data[11]
* Pin 14: 0V
* Pin 15: 0V

'''Note''': Please see the [http://files.ettus.com/manual/page_gpio_api.html E3x0/X3x0 GPIO API] for information on configuring and using the GPIO bus.

===On-Board LEDs===
{| class="wikitable"

!LED
!Detail
!Description
|-

| DS1
| 1.2V
| Power
|-

| DS2
| TXRX1
| Red: TX, Green: RX
|-

| DS3
| RX1
| Green: RX
|-

| DS4
| REF
| Reference Lock
|-

| DS5
| PPS
| Flashes on Edge
|-

| DS6
| GPS
| GPS Lock
|-

| DS7
| SFP0
| Link, Right, Green
|-

| DS8
| SFP0
| Link Activity, Left, Yellow
|-

| DS10
| TXRX2
| Red: TX Green: RX
|-

| DS11
| RX2
| Green: RX
|-

| DS12
| 6V
| Daughterboard Power
|-

| DS13
| 3.8V
| Power
|-

| DS14
| 3.3V
| Management Power
|-

| DS15
| 3.3V
| Auxiliary Management Power
|-

| DS16
| 3.3V
| FPGA Power
|-

| DS19
| SFP1
| Link Active, Left, Yellow
|-

| DS20
| SFP1
| Link, Right, Green
|-

| DS21
| LINK
| Link Activity
|-

|}

===Power Connector===
Model: PDP-40 by CUI Inc.

Power plug connectors for custom power harnesses can be purchased here: https://www.digikey.com/products/en?KeyWords=CP-7340-ND&WT.z_cid=sp_102_buynow

Assembly instructions: [[Media:pdp-40.pdf]]

====Pin Detail====
* Pins #1 / #2: 12v
* Pins #3 / #4: Ground

[[File:pdp 40 power detail.png]]

==Certifications==
===RoHS===
As of December 1st, 2010 all Ettus Research products are RoHS compliant unless otherwise noted. More information can be found at [http://ettus.com/legal/rohs-information http://ettus.com/legal/rohs-information]

===China RoHS===
'''Management Methods for Controlling Pollution Caused by Electronic Information Products Regulation'''

'''Chinese Customers'''

National Instruments is in compliance with the Chinese policy on the Restriction of Hazardous Substances (RoHS) used in Electronic Information Products. For more information about the National Instruments China RoHS compliance, visit [http://www.ni.com/environment/rohs_china ni.com/environment/rohs_china].

==Certificate of Volatility==

Found on the [https://www.ni.com/en/support/documentation/product-certifications.html NI Product Certifications lookup tool] [https://www.ni.com/pdf/manuals/377356a.pdf here].

==Downloads==
[http://files.ettus.com/manual/md_fpga.html FPGA Resources]

[http://files.ettus.com/binaries/uhd_stable/ UHD Stable Binaries]

[https://github.com/EttusResearch/uhd UHD Source Code on Github]

==Choosing USRP X310 vs USRP X300==
In terms of host bandwidth, interface options, and all other hardware features the USRP X300 and USRP 310 are identical. However, the USRP X310 provides a larger FPGA, a Xilinx XC7K410T, as opposed to XC7K325T. While both options provide a significant amount of free resources for custom FPGA development, the XC7K410T provides additional design margin, which translates to ease of development and future expandability. Most users choose the USRP X310 for their development.

{| class="wikitable" style="margin: auto;"
!colspan="3"|USRP X300 and X310 FPGA Resource Summary
|-
|rowspan="2"|Resource Type
|USRP X300 (XC7K325T)
|USRP X310 (XC7K410T)
|-
|Count
|Count
|-
|DSP48 Blocks
|840
|1540
|-
|Block Rams (18kB)
|890
|1590
|-
|Logic Cells
|326,080
|406,720
|-
|Slices (logic)
|50,950
|63,550
|-
|}

For up-to-date information on FPGA resource utilization in the stock FPGA design, please see "USRP 300/X310 FPGA Resources" in the Ettus Research knowledge base (https://kb.ettus.com).

==Choosing an RF Daughterboard==
With the increased sample rates used by the USRP X300 and USRP X310, these new device can support extended-bandwidth daughterboards. The WBX-120, SBX-120, and CBX-120 are recommended to take advantage of the full bandwidth capability of the USRP X300 and X310. The WBX-120, SBX-120, and CBX-120 have been upgraded from their predecessors (40 MHz) to use 120 MHz baseband filters. You can select your daughterboard based on the center frequency of your primary application.

{| class="wikitable" style="margin: auto;"
!Daughterboard
!Frequency Range
!Bandwidth
|-

|WBX-120
|50 MHz - 2200 MHz
|120 MHz
|-

|SBX-120
|400 MHz - 4400 MHz
|120 MHz
|-

|CBX-120
|1200 MHz - 6000 MHz
|120 MHz
|-

|UBX-160
|10 MHz - 6000 MHz
|160 MHz
|-

|TwinRX
|10 MHz - 6000 MHz
|80 MHz per channel, 160 MHz total
|-

|}

If your application is in the HF frequency range, the LFRX and LFTX are recommended for up to 30 MHz of bandwidth per channel. The BasicRX and BasicTX are ideal for configurations that use an external frontend for tuning and filtering with either an IF or baseband interface.

The USRP X300 and X310 are backward compatible with legacy daughterboards except for the RFX Series and XCVR2450. Please note, while there are two daughterboard slots, the USRP X300/X310 can only support a single TVRX2.

If you plan to transmit or receive over the air, you should also purchase an antenna.

==Choosing a Host Interface==

The USRP X300/X310 provide three interface options – 1 Gigabit Ethernet (1 GigE), 10 Gigabit Ethernet (10 GigE), and PCI-Express (PCIe). The PCIe interface is always available regardless of what FPGA image is loaded. Ettus ships two FPGA image variants, the HG or HGS image which has one 1 GigE interfaces and one 10 GigE interfaces, and the XG image which has two 10 GigE interfaces. Generally, Ettus Research recommends using 10 GigE to achieve the maximum throughput available from the USRP X300/X310. PCIe is recommended for applications that require the lowest possible latency, which is a desirable characteristic for PHY/MAC research. If your application does not require the full bandwidth of the USRP ™ X300 and X310, the 1 GigE interface serves as a cost-effective fall-back option. Ettus Research provides a complete interface kit for each of these options, which is also shown in Table 3.

{| class="wikitable" style="margin: auto;"
!colspan="4"|Table 3 - Interface Performance Summary
|-
!Interface
!Throughput (MS/s @ 16-bit)
!Target
!Recommended Kit
|-
|1 Gigabit
|25 MS/s
|Desktop/Laptop
|Components provided with USRP X300/X310 kit.
For additional connections, purchase the following:
[https://www.ettus.com/product/details/1GIGE-KIT SFP Adapter + GigE Cable]
|-
|10 Gigabit
|200 MS/s
|Desktop
|[https://www.ettus.com/product/details/10GIGE-KIT 10 GigE Interface Kit]
|-
|PCI-Express
(PCIe, 4 lane)
|200 MS/S
|Desktop
|[https://www.ettus.com/product/details/PCIE-KIT PCI-Express Desktop Kit]
|-
|Express Card
(PCIe, 1 lane)
|50 MS/s
|Laptop
|[https://www.ettus.com/product/details/ECARD-KIT ExpressCard Kit]
|-
|}

[[File:Connectivity 2.png|700px|center]]

<center>Figure 2 - Host Interface Options</center>

===10 Gigabit Ethernet===
See [https://kb.ettus.com/Using_Dual_10_Gigabit_Ethernet_on_the_USRP_X300/X310 this app note] for how to use the X3x0 with dual 10 GbE links.

'''Recommended 10 Gigabit Ethernet Cards'''
* Intel X520-DA2
** [http://ark.intel.com/products/39776/Intel-Ethernet-Converged-Network-Adapter-X520-DA2 Intel® Ethernet Converged Network Adapter X520-DA2]
* Intel X520-DA1
** [http://ark.intel.com/products/68669/Intel-Ethernet-Converged-Network-Adapter-X520-DA1 Intel® Ethernet Converged Network Adapter X520-DA1 ]
* Intel X710-DA2
** [http://ark.intel.com/products/83964/Intel-Ethernet-Converged-Network-Adapter-X710-DA2 Intel® Ethernet Converged Network Adapter X710-DA2 ]
* Intel X710-DA4
** [http://ark.intel.com/products/83965/Intel-Ethernet-Converged-Network-Adapter-X710-DA4 Intel® Ethernet Converged Network Adapter X710-DA4 ]
* Mellanox MCX4121A-ACAT
** [https://store.mellanox.com/products/mellanox-mcx4121a-acat-connectx-4-lx-en-network-interface-card-25gbe-dual-port-sfp28-pcie3-0-x8-rohs-r6.html Mellanox MCX4121A-ACAT ]

==International Power Supply Options==
The power supply provided with the USRP X300/X310 kit is packaged with a power cord that is compatible with power outlets in the US/Japan. If you are not using the USRP X300/X310 in the US/Japan, we recommend purchasing the International USRP X300/X310 Power Cord set.

==Option: GPS Disciplined, Oven-Controlled Oscillator (GPSDO)==
The USRP X300 and USRP X310 provide the option to integrate a high-accuracy GPS-disciplined oscillator (GPSDO). The GPSDO improves the accuracy of the internal frequency reference to 20 ppb, or 0.1 ppb if the GPS is synchronized to the GPS constellation. When synchronized to the GPS constellation, all USRP ™ devices will also be synchronized in time within 50 ns.

{| class="wikitable" style="margin: auto;"
|
!Internal TCXO
!GPS-Disciplined Clock
|-
|Frequency Reference
|TCXO
|OCXO
|-
|Frequency Accuracy (unlocked)
|± 2.5ppm
± 2,500 Hz @ 1 GHz
|± 25 ppb
± 25 Hz @ 1 GHz
|-
|Frequency Accuracy
|
|± 0.01ppb
|-
|(GPS-Disciplined)
|
|~ ± 0.01 Hz @ 1 GHz
|-
|GPS Time Sync Accuracy
|
|±50ns to UTC Time**
|-
|10 MHz Reference Phase Drift with GPS Sync
|
|<±20ns After 1 Hour**
|-
|}

==Option: Antenna Kit for GPSDO==
The GPSDO Mini Kit will improve the accuracy of the USRP reference clock, even if it does not receive signals from the GPS Constellation. However, to achieve the best accuracy possible, and to achieve global timing alignment across multiple USRPs, Ettus Research recommends the GPSDO Mini Antenna Kit.

==Option: General Purpose Input/Output (GPIO) Kit==
The USRP X300 and X310 include a DB15 connector on the front panel that provides convenient access to GPIO signals. Each pin can be configured as an input or output, uses 3.3V-level logic, and is protected with basic anti-static circuitry. These pins can be used to control external devices like RF switches and amplifiers, trigger software events on the host, or even provide basic debugging functionality. The USRP GPIO Kit is an affordable option that provides access to these signals with a DB15 cable and a breakout board. The breakout board allows the user to connect external devices through a terminal block. The user can also solder wires and components into the dedicated prototyping area.

==Option: Cables for MIMO Expansion==
Multiple USRP X300/X310s can be synchronized for coherent operation by sharing a common 10 MHz and 1 PPS signal. We recommend using a star-distribution topology with an OctoClock or OctoClock-G, as seen in Figure 4. This requires matched length cables to be used for both 10 MHz and 1 PPS.

For more information about MIMO operation, please see the MIMO and Synchronization Application Note.
[[File:8mimo.png|700px|center]]
<center>Figure 4 - Star-Distribution of 10 MHz/PPS Signals with OctoClock</center>

==Option: USRP X300/X310 Rackmount==

The USRP X300 and X310 were designed to be used with a [https://www.ettus.com/all-products/rackmount-1u/ 1U Rackmount Assembly] for building high-density MIMO systems in a compact and well-organized setup. This mount supports one or two compatible USRPs, and if two are mounted then there are rubber standoffs between the USRPs to avoid both direct contact and surface scratching. If the user will be developing in a laboratory environment or building a high-channel count USRP system, then a 1U Rackmount Assembly is highly recommended. This specific mount is compatible with only the USRP X300 and X310, and allows the integration of up to four bidirectional -- or eight receive-only -- RF channels per 1U.

==Guidance on SFP+ Adapters for Fiber Connectivity on USRP X300/X310==

Ettus Research currently offers direct-connect, copper cabling accessories for the USRP X300 and USRP X310. However, it is also possible to use multi-mode fiber instead of copper connections for these devices.

The USRP X Series is compatible with most brands of SFP+ fiber adapters. In some cases, other equipment in the systems such as 1/10 Gigabith Ethernet switches are only compatible with specific brands of SFP+ adapters and cables. As a general rule, we recommend checking compatibility with the switches and network cards in your system before purchasing an adapter.

Ettus Research does test the USRP X Series devices with our [https://www.ettus.com/product/details/10GIGE-KIT 10 Gigabit Ethernet Connectivity Kit] and a Blade Networks G8124 1/10 GigE switch. Here are is a list of known-good cables and adapters.

Ettus Research has only tested multi-mode fiber accessories.

===Known-Good Adapters===
* [https://approvedoptics.com/blade-networks-bn-ckm-sp-sr/ Approved Optics Blade Networks BN-CKM-SP-SR-A]

===Known-Good Cables===
* [https://www.colfaxdirect.com/store/pc/viewPrd.asp?idproduct=995&idcategory=2 Myricom Fiber Cables for 10GBase-SR, 3 Meters 10G-SR-3M]

==Guidance on 10Gb SFP+ to RJ45 Adapters==

Many new motherboards come equipped with an onboard 10Gb RJ45 NIC. It is possible to use a SFP+ to RJ45 adapter and operate at 10Gb speeds using a Cat6/7 Ethernet cables.

Ettus Research has tested the adapters linked below.

===Known-Good Adapters===
* [https://www.amazon.com/10Gtek-SFP-10G-T-S-Compatible-10GBase-T-Transceiver/dp/B01KFBFL16/ 10Gtek SFP+ to RJ45 Copper Module]
* [https://www.prolabs.com/products/transceivers/brocade/sfpplus/100-1000-10000base/10g-sfpp-t-c ProLabs 10G-SFPP-T-C]

==FAQ==
USRP™ X300 and USRP™ X310 SDRs Frequently Asked Questions

* '''What is the bandwidth of the USRP X300/X310'''

The ADC rate on each analog RX channel is 200 MS/s quadrature, which provides a theoretical analog bandwidth of approximately 80% of the Nyquist bandwidth of +/- 100 MHz (+/- 80 MHz around the center frequency). The resulting maximum theoretical analog bandwidth is 160 MHz. The actual analog bandwidth may be reduced due the RF daughterboard selected.

RF Daughterboard Bandwidths: See the daughterboard specifications [link]

FPGA Processing Bandwidth: Up to 200 MS/s quadrature.

Host Bandwidth: Up to 200 MS/s quadrature, dependent on selected interface

For more information about achieving the maximum bandwidth with a USRP X300/X310, please see the "USRP X300/X310 Configuration Guide" or the "USRP System Bandwidth" application note.

* '''How can I program the USRP X300/X310'''

Like all other USRP models, the USRP X300 and X310 are compatible with the USRP Hardware Driver™ (UHD) architecture. The UHD architecture is a common driver that allows users to develop and execute applications on a host-PC. UHD provides a direct C++ API to control and stream to/from the USRP X300/X310. It also provides compatibility with a variety of third-party software frameworks including GNU Radio, LabVIEW, and Matlab. You may also customize the FPGA image provided with UHD to integrate your own signal processing. For more information about UHD, and supported software frameworks, please see:

http://files.ettus.com/manual/

* '''How do I update the FPGA images and firmware with the latest from UHD'''

You can find more information about updating the FPGA image in the UHD manual: https://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_getting_started_fpga_update

* '''How can I modify the FPGA of the USRP X300/X310'''

The source code (Verilog) for the USRP X300/X310 is available in the UHD repository. The build process leverages the existing CMAKE build system used to compile the host-side driver. A Linux-based setup will provide the best results.

Which FPGA toolchain required to build the FPGA images will depend upon your version of UHD. For more details please see the [[UHD]] Software Resource page.

* '''How much free space is available in the USRP X300/X310 FPGA'''

Please see the USRP X300/X310 FPGA resources page for more information.

* '''What type of PC setup is recommended for use with the USRP X300/X310'''

The type of PC required depends heavily on the complexity and bandwidth of the application. To demonstrate the USRP X300/X310, we typically use a desktop computer with a quadcore i7, 8+ GB of DDR3, and install the PCIe interface card that is also provide with the 10 GigE, PCIe, and ExpressCard interface kits.

* '''What frequency range does the USRP X300/X310 cover'''

The frequency range depends on the daughterboard select by the users. For more information, please see the USRP X300/X310 Configuration Guide.

* '''What components do I need to purchase for a complete USRP X300/X310 system'''

For a more comprehensive guide, please see the USRP X300/X310 Configuration Guide.

* '''What is the difference between the USRP X300/X310'''

The USRP X310 includes a larger Kintex-7 series FPGA (XC7K410T) with additional development resources for more complex designs. The USRP X300 includes the smaller XC7K325T FPGA.

* '''What is the part number of the X300/X310 power connector'''
Model: PDP-40 by CUI Inc.
Power plug connectors for custom power harnesses can be purchased here: https://www.digikey.com/products/en?KeyWords=CP-7340-ND&WT.z_cid=sp_102_buynow

[[Category:Hardware Resources]]

File:cu x3xx motherboard cca2.stp

2025-03-20T21:47:14Z

DylanCaswell:

USRP-2974

2025-01-15T18:09:11Z

DylanCaswell: /* Rear Panel */

== Device Overview ==
The NI USRP-2974 is a high-performance, USRP software defined radio (SDR) stand-alone device for designing and deploying next generation wireless communications systems. The hardware architecture combines two extended-bandwidth daughterboard slots covering 10 MHz – 6 GHz with up to 160 MHz of baseband bandwidth, multiple high-speed interface options (PCIe, dual 10 GigE), an onboard Intel Core i7 processor, and a large user-programmable Kintex-7 FPGA in a convenient desktop or rack-mountable half-wide 2U form factor.

The USRP-2974 is the equivalent to a USRP X310 with two UBX-160 boards, a GPSDO and an onboard Intel i7 computer. The USRP-2974 comes with NI Linux RTOS pre-installed, but in order to use it with open-source tool-chain, a user will need to install Linux (preferably Fedora or Ubuntu) and then the USRP Hardware driver (UHD). After these have been installed, any other open-source tools can be installed, such as GNU Radio.

== Key Features of the USRP-2974==
{|
|style="vertical-align:top"|
* Intel Core i7 6822EQ 2GHz Quad CoreProcessor
* 16GB DDR4 Memory
* 512GB SSD
* USB-to-UART to the CPU
* Xilinx Kintex-7 XC7K410T FPGA
* 14 bit 200 MS/s ADC
* 16 bit 800 MS/s DAC
* Frequency range: 10 MHz - 6 GHz
* Up 160MHz<sup>*</sup> bandwidth per channel
* 2 Transmit ports
* 2 Receive ports
* GPSDO
* Multiple high-speed interfaces (Dual 10G, PCIe Express, 1G)
|[[File:USRP_2974_frt_dia.jpg|350px|center]]
|}

== Controller - Onboard computer ==
{| class="wikitable"

|System on module (SoM)
|Congatec COM Express conga-TS170
|-

|CPU
|Intel Core i7 6822EQ (2 GHz Quad Core)
|-

|Memory
|SO-DIMM DDR4 16 GB
|-

|SFP+<sup>1</sup>
|10G ETH connection to the SoM
|-

|Cabled PCIe
|PCIe Gen 2 x4
|-

|MicroUSB<sup>2</sup>
|USB-to-UART to the SoM
|-

|RJ45
|1G ETH host connection
|-

|}

<sup>1</sup> Can be bypassed to the FPGA.

<sup>2</sup> Device port for external host.

 
<br>
 

==RF Specifications==

{| class="wikitable"
|-
!colspan="2"|Transmitter
|-
|Number of channels
|2
|-
|Frequency range
|10 MHz to 6 GHz
|-
|Frequency step
|<1kHz
|-
|Maximum output power
|5 mW to 100 mW (7 dBm to 20 dBm)
|-
|Gain range<sup>1</sup>
|0 dB to 31.5 dB
|-
|Gain step
|0.5 dB
|-
|Maximum instantaneous real-time bandwidth
|160 MHz
|-
|}

{| class="wikitable"
|-
!colspan="2"|Receiver
|-
|Number of channels
|2
|-
|Frequency range
|10 MHz to 6 GHz
|-
|Frequency step
|<1 kHz
|-
|Gain range<sup>2</sup>
|0 dB to 37.5 dB
|-
|Gain step
|0.5 dB
|-
|Maximum input power
| -15 dBm
|-
|Noise Figure
|5 dB to 7 dB
|-
|Maximum instantaneous real-time bandwidth<sup>3</sup>
|160MHz                                        
|-
|}
<sup>1</sup> The output power resulting from the gain setting varies over the frequency band and among
devices.

<sup>2</sup>The received signal amplitude resulting from the gain setting varies over the frequency band and
among devices.

<sup>3</sup>The USRP-2974 receiver path has 84 MHz of bandwidth for center frequencies from 10 MHz to
500 MHz

'''NOTE:''' As mentioned earlier, the USRP-2974 incorporates 2 UBX-160 daughterboards. Therefore, for more information on RF performance, please see the [[UBX | UBX hardware resource]] page

==Hardware Specifications==
===USRP Hardware Driver (UHD) version===
* Minimum version of UHD required: '''3.14.1.0'''

===Clocking and Sampling Rates===
There are two master clock rates (MCR) supported on the USRP-2974 like on the X310: 200.0 MHz and 184.32 MHz.

The sampling rate must be an integer decimation rate of the MCR. Ideally, this decimation factor should be an even number. An odd decimation factor will result in additional unwanted attenuation (roll-off from the CIC filter in the DUC and DDC blocks in the FPGA). The valid decimation rates are between 1 and 1024.

For the MCR of 200.0 MHz, the achievable sampling rates using an even decimation factor are 200.0, 100.0, 50.0, 33.33, 25.0, 20.0, 16.67, 14.286 Msps, ... 195.31 Ksps.

For the MCR of 184.32 MHz, the achievable sampling rates using an even decimation factor are 184.32, 92.16, 46.08, 30.72, 23.04, 18.432, 15.36, 13.166 Msps, ... 180.0 Ksps.

If the desired sampling rate is not directly supported by the hardware, then it will be necessary to re-sample in software. This can be done in C++ using libraries such as Liquid DSP [https://github.com/jgaeddert/liquid-dsp], or can be done in GNU Radio, in which there are three blocks that perform sampling rate conversion.

==Physical Specifications==

===Dimensions===
(L × W × H) 29.08 cm × 21.84 cm × 7.98 cm (11.45 in. × 8.60 in. × 3.14 in. )

===Weight===
3.34 kg (7.35 lb)

==Power==
{| class="wikitable"

|Voltage range
|14.25 V to 15.75 V DC
|-

|Current
|10 A, maximum
|-

|Power
|150 W, maximum
|-

|}

==Environmental Specifications==

'''NOTE:''' Indoor use only

===Operating Temperature Range===
* 0 °C to 50 °C

===Maximum altitude===
* 2,000 m (800 mbar) (at 25 °C ambient temperature)

===Operating Humidity Range===
* 10% to 90% non-condensing

===Pollution Degree===
* 2

==System Diagram and Schematics==

===System Block Diagrams===
[[file:2974_blk_dia_hiLevel_v01.png | 800px]]
<center>High Level Block Diagram of the USRP 2974</center>

[[file:2974_blk_dia.png |800px]]

<center>[http://www.ni.com/documentation/en/usrp-software-defined-radio-stand-alone-device/latest/usrp-2974/block-diagram/ Detailed System Block Diagram]</center>

===Schematics===
Because the USRP-2974 is a combination of an Intel i7 SOM and an X310 USRP, a user can reference the X310 Schematics.

[http://files.ettus.com/schematics/x300/x3xx.pdf X310 Schematics]

==Key Component Datasheets==
{| class="wikitable" style="width:80%"
!Part Number
!Description
!Schematic ID (Page)
|-

|[https://www.congatec.com/fileadmin/user_upload/Documents/Datasheets/conga-TS170.pdf conga-TS170]
|System on Module (SoM)
|
|-

|[http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf XC7K410T]
|FPGA
|U23 (3,5,8,9,10,18)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/AD9146.PDF AD9146]
|Dual Channel, 16-Bit, 1230 MSPS DAC
|U12, U36 (7)
|-

|[http://www.ti.com/lit/ds/slas635b/slas635b.pdf ADS62P48]
|Dual Channel, 14-Bit 210 MSPS ADC
|U11, U35 (6)
|-

|[https://www.onsemi.com/pub/Collateral/FIN1002-D.pdf FIN1002]
|High Speed Differential Receiver
|U3, U5, U31, U32 (4)
|-

|[http://ww1.microchip.com/downloads/en/DeviceDoc/20001203U.pdf 24LC256T]
|EEPROM
|U530 (11)
|-

|[http://www.ti.com/lit/ds/symlink/lmk04816.pdf LMK04816BISQ/NOPB_1/3]
|Jitter Cleaner With Dual Loop PLLs
|U531 (11)
|-

|[http://ww1.microchip.com/downloads/en/DeviceDoc/sy89547l.pdf SY89547LMGTR]
|Multiplexer
|U506 (12)
|-

|[http://www.ti.com/lit/ds/symlink/sn74aup1t17.pdf SN74AUP1T17]
|Single Schmitt-Trigger Buffer Gate
|U6, U519 (12)
|-

|[http://www.ti.com/lit/ds/symlink/tps54620.pdf TPS54620RGYT]
|Synchronous Step Down SWIFT™ Converter
|U515 (21); U516 (26)
|-

|[http://cds.linear.com/docs/en/datasheet/1764fb.pdf LT1764EQ-3.3]
|Voltage Regulator
|U27 (21); U516 (26)
|-

|[http://www.ti.com/lit/ds/symlink/tps7a47.pdf TPS7A47]
|Voltage Regulator
|U28, U532 (21)
|-

|[http://cds.linear.com/docs/en/datasheet/3603fc.pdf LTC3603EUF_TRPBF]
|Monolithic Synchronous Step-Down Regulator
|U517 (23); U500 (25); U514, U513 (27)
|-

|[http://www.ti.com/product/TPS77625-EP?keyMatch=TPS77625&tisearch=Search-EN-Everything TPS77625]
|Low-Dropout Voltage Regulators
|U30 (23)
|-

|[http://www.ti.com/lit/ds/symlink/tps79318-ep.pdf TPS79318_SM]
|Low-Dropout Voltage Regulators
|U510 (27)
|-

|[[Media:agile9598503.pdf|OSC-96MHZ-724821-01]]
|Voltage Controlled Crystal Oscillator
|U25 (11)
|-

|}

==FPGA and Baseband==

{| class="wikitable"

|FPGA
|Kintex-7 XC7K410T
|-

|DRAM
|1 GB
|-

|Baseband analog-to-digital converter
(ADC) resolution
|14 bit
|-

|Baseband digital-to-analog converter
(DAC) resolution
|16 bit
|-

|ADC spurious-free dynamic range (sFDR)
|88 dB
|-

|DAC sFDR
|80 dB
|-

|Maximum I/Q sample rate
|200 MS/s
|-

|SFP+<sup>1</sup>
|High speed serial link to one of the FPGA
GTX transceivers
|-

|}

<sup>1</sup>Can be bypassed to the SoM if using the 10 GbE as protocol.

===FPGA User Modifications===

The Verilog code for the FPGA in the NI USRP-2974 is open-source, and users are free to modify and customize it for their needs. However, certain modifications may result in either bricking the device, or even in physical damage to the unit. Specifically, changing the I/O interface of the FPGA in any way (do not remove any of the I/O for the PCIe interface, such as <code>x300_pcie_int</code> and <code>LvFpga_Chinch_Interface</code>), or modifying the pin and timing constraint files, could result in physical damage to other components on the motherboard, external to the FPGA, and doing this will void the warranty. Also, even if the PCIe interface is not being used, you cannot remove or reassign these pins in the constraint file. The constraint files should not be modified. Please note that modifications to the FPGA are made at the risk of the user, and may not be covered by the warranty of the device.

==Interfaces and Connectivity==
Follow the links below for additional information on configuring each interface for the USRP-2974.

*[http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_10gige Dual 10 Gigabit Ethernet] - 200 MS/s Full Duplex @ 16-bit
*[http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_pcie PCIe Express (Desktop)] - 200 MS/s Full Duplex @ 16-bit
*[http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_1gige 1 Gigabit Ethernet] - 25 MS/s Full Duplex @ 16-bit

===Front Panel===

[[File:USRP-2974 Front Panel.jpg|800px]]
[[File:2974_frt_wireframe.png|800px]]

{| class="wikitable"
!Connector
!colspan="2" | '''Use'''
|-
|rowspan="2" | RF 0
|TX1<p>RX1</p>
|Input and output terminal for the RF signal. TX1 RX1 is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input or output channel.
|-
|RX2
|Input terminal for the RF signal. RX2 is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input channel.
|-

|colspan="2" | AUX I/O
|General-purpose I/O (GPIO) port. AUX I/O is controlled by the FPGA.
|-

|rowspan="2" | RF 1
|TX1<p>RX1</p>
|Input and output terminal for the RF signal. TX1 RX1 is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input or output channel.
|-
|RX2
|Input terminal for the RF signal. RX2 is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input channel.
|-

|colspan="2" | DP
|DisplayPort connector to connect one monitor for your controller.
|-

|colspan="2" | USB2.0
|USB ports that support common USB peripheral devices such as flash drives, hard drives, keyboards, and mice.
|-

|colspan="2" | USB3.0
|USB ports that support common USB peripheral devices such as flash drives, hard drives, keyboards, and mice.
|-

|colspan="2" | 1G ETH
|RJ45 port used for 1G ETH connectivity to other ethernet devices.
|-

|colspan="2" | μUSB
|USB port used for UART connectivity to the controller.
|-

|colspan="2" | 1G/10G ETH 0
|SFP+ port used for 10G ETH connectivity to other ethernet devices. Connects to the embedded Linux computer for communication with LabVIEW RT.
|-

|colspan="2" | 1G/10G ETH 1
|SFP+ port used for 1G/10G ETH connectivity to other ethernet devices. Connects to the FPGA. Not currently supported in LabVIEW Communications System Design Suite.
|-

|}

{| class="wikitable"
!colspan="2" | '''LED'''
!'''Description'''
!'''Color'''
!'''State'''
!'''Indication'''
|-
|rowspan="5" | RF 0
|rowspan="3" | TX1<p>RX1</p>
|rowspan="3" | Indicates thetransmit status of the device
|OFF
| —
|The device is not active.
|-
|Red
|Solid
|The device is transmitting data.
|-
|Green
|Solid
|The device is receiving data.
|-
|rowspan="2" | RX2
|rowspan="2" | Indicates the receive status of the device.
|OFF
| —
|The device is not receiving data.
|-
|Green
|Solid
|The device is receiving data.
|-

|rowspan="3" colspan="2"| REF
|rowspan="3" | Indicates the status of the reference signal.
|OFF
| —
|There is no reference signal, or the device is not locked to the reference signal.
|-
|rowspan="2" |Green
|Blinking
|The device is not locked to the reference signal.
|-
|Solid
|The device is locked to the reference signal.
|-

|rowspan="2" colspan="2"| PPS
|rowspan="2" | Indicates the pulse per second (PPS).
|OFF
| —
|There is no PPS timing reference signal, or the device is not locked to the reference signal.
|-
|Green
|Blinking
|The device is locked to the PPS timing reference signal.
|-

|rowspan="2" colspan="2"| GPS
|rowspan="2" | Indicates whether the GPSDO is locked.
|OFF
| —
|There is no GPSDO or the GPSDO is not locked.
|-
|Green
|Solid
|The GPSDO is locked.
|-

|rowspan="5" | RF 1
|rowspan="3" | TX1<p>RX1</p>
|rowspan="3" | Indicates thetransmit status of the device
|OFF
| —
|The device is not active.
|-
|Red
|Solid
|The device is transmitting data.
|-
|Green
|Solid
|The device is receiving data.
|-
|rowspan="2" | RX2
|rowspan="2" | Indicates the receive status of the device.
|OFF
| —
|The device is not receiving data.
|-
|Green
|Solid
|The device is receiving data.
|-

|rowspan="2" colspan="2"| Status
|rowspan="2" | Indicates the status of the device
|OFF
| —
|The device initialized successfully and is ready for use.
|-
|Red
|Blinking
|Hardware error. An internal power supply has failed. Check front-panel I/O connections for shorts. Remove any shorts and cycle power to the USRP-2974. Contact NI if the problem persists.
|-

|rowspan="2" colspan="2"| PWR
|rowspan="2" | Indicates the power status of the device
|OFF
| —
|The device is powered off.
|-
|Green
|Solid
|The devices is powered on.
|-

| rowspan="3" colspan="2" | 10/100/1000
| rowspan="3"| Indicates the speed of the Gigabit Ethernet link.
|OFF
| —
|No link, or 10 Mbps link.
|-
|Green
|Solid
|100 Mbps link.
|-
|Amber
|Solid
|1,000 Mbps link.
|-

| rowspan="3" colspan="2"| ACT/LINK
| rowspan="3" | Indicates the Gigabit Ethernet link activity or status.
|OFF
| —
|No link has been established.
|-
| rowspan="2" | Green
|Solid
|A link has been negotiated.
|-
|Blinking
|Activity on the link.
|-

| rowspan="5" | 1G/10G ETH 0
| rowspan="3" | ACT/LINK
| rowspan="3" | Indicates the status of the SFP+ port.
|OFF
| —
|The link is down.
|-
| rowspan="2" |Green
|Solid
|The link is up.
|-
|Blinking
|The link is active (transmitting and receiving).
|-
| rowspan="2" |10GbE
| rowspan="2" |Indicates the status of the 10G ETH link.
|OFF
| —
|The 10G ETH link is down.
|-
|Green
|Solid
|The 10G ETH link is up.
|-

| rowspan="2" colspan="2" | 1G/10G ETH 1 10GbE
| rowspan="2" | Indicates the status of the 10G ETH link.
|OFF
| —
|The 10G ETH link is down.
|-
|Green
|Solid
|The 10G ETH link is up.
|-

|}

===Rear Panel===
[[File:USRP-2974 Rear Panel.jpg|800px]]
[[File:2974_back_wireframe.png|800px]]

{| class="wikitable"
!Connector
!Use
|-
|REF OUT
|Output terminal for an external reference signal for the LO on the device. REF OUT is an SMA (f) connector with an impedance of 50 Ω, and it is a single-ended reference output. The output signal at this connector is 10 MHz at 3.3 V.
|-

|REF IN
|Input terminal for an external reference signal for the LO on the device. REF IN is an SMA (f) connector with an impedance of 50 Ω, and it is a single-ended reference input. REF IN accepts a 10 MHz signal with a minimum input power of 0 dBm (0.632 Vpk-pk) and a maximum input power of 15 dBm (3.56 Vpk-pk), The optimal signal is a square wave.
|-

|PPS TRIG OUT
|Output terminal for the PPS timing reference. PPS TRIG OUT is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input. The output signal is 0 V to 3.3 V TTL. You can also use this port as a triggered output (TRIG OUT) that you program with the PPS Trig Out I/O signal.
|-

|PPS TRIG IN
|Input terminal for PPS timing reference. PPS TRIG IN is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input channel. PPS TRIG IN accepts 0 V to 3.3 V TTL and 0 V to 5 V TTL signals. You can also use this port as a triggered input (TRIG IN) that you control using NI-USRP software.
|-

|GPS ANT
|Input terminal for the GPS antenna signal. GPS ANT is an SMA (f) connector with a maximum input power of -15 dBm and an output of DC 5 V to power an active antenna. <p> '''Notice:''' Do not terminate the GPS ANT port if you do not use it.
|-

|PCIe x4
|Port for a PCIe connection through an MXI Express cable. Can be used to connect an external USRP device.
|-

|SYSTEM POWER IN
|Input that accepts a 15 V ± 5%, 10 A external DC power connector.
|-

|}

===Ref Clock - 10 MHz===

An external 10 MHz reference clock may be used. The optimal signal is a square wave as created by the [https://kb.ettus.com/OctoClock_CDA-2990 OctoClock/CDDA-2990]. The input signal power level of the reference clock must not exceed +15 dBm.

===PPS - Pulse Per Second===
Using a PPS signal for timestamp synchronization requires a square wave signal with the following a 5Vpp amplitude.

To test the PPS input, you can use the following tool from the UHD examples:

* <code><args></code> are device address arguments (optional if only one USRP device is on your machine)

cd <install-path>/lib/uhd/examples ./test_pps_input –args=<args>

===Front Panel GPIO===
{|
| style="width:50%" |
The GPIO port is not meant to drive big loads. You should not try to source more than 5mA per pin.

The +3.3V is for ESD clamping purposes only and not designed to deliver high currents.

| style="vertical-align:top" | [[File:x3x0 gpio conn.png]]
|}

====Power on state====
The hardware power on state and UHD initial state for the front-panel GPIOs is high-Z. For the X3xx, there are no external pull-ups/pull-downs for the GPIO pins, but the FPGAs do have them and they are configured as follows: X3xx: pull-down.

====Pin Mapping====
* Pin 1: +3.3V
* Pin 2: Data[0]
* Pin 3: Data[1]
* Pin 4: Data[2]
* Pin 5: Data[3]
* Pin 6: Data[4]
* Pin 7: Data[5]
* Pin 8: Data[6]
* Pin 9: Data[7]
* Pin 10: Data[8]
* Pin 11: Data[9]
* Pin 12: Data[10]
* Pin 13: Data[11]
* Pin 14: 0V
* Pin 15: 0V

'''Note''': Please see the [http://files.ettus.com/manual/page_gpio_api.html E3x0/X3x0 GPIO API] for information on configuring and using the GPIO bus.

==Certifications==
===RoHS===
As of December 1st, 2010 all NI/Ettus Research products are RoHS compliant unless otherwise noted. More information can be found at [http://ettus.com/legal/rohs-information http://ettus.com/legal/rohs-information]

===China RoHS===
'''Management Methods for Controlling Pollution Caused by Electronic Information Products Regulation'''

'''Chinese Customers'''

National Instruments is in compliance with the Chinese policy on the Restriction of Hazardous Substances (RoHS) used in Electronic Information Products. For more information about the National Instruments China RoHS compliance, visit [http://www.ni.com/environment/rohs_china ni.com/environment/rohs_china].

==Downloads==
[http://files.ettus.com/manual/md_fpga.html FPGA Resources]

[http://files.ettus.com/binaries/uhd_stable/ UHD Stable Binaries]

[https://github.com/EttusResearch/uhd UHD Source Code on Github]

==Choosing an Interface==

The USRP-2974 provides three interface options – 1 Gigabit Ethernet (1 GigE), 10 Gigabit Ethernet (10 GigE), and PCI-Express (PCIe). The PCIe interface is always available regardless of what FPGA image is loaded. Ettus ships two FPGA image variants, the HG or HGS image which has one 1 GigE interfaces and one 10 GigE interfaces, and the XG image which has two 10 GigE interfaces. Generally, Ettus Research recommends using 10 GigE to achieve the maximum throughput available from the USRP-2974. PCIe is recommended for applications that require the lowest possible latency, which is a desirable characteristic for PHY/MAC research. If your application does not require the full bandwidth of the USRP-2974, the 1 GigE interface serves as a cost-effective fall-back option. Ettus Research provides a complete interface kit for each of these options, which is also shown in the following table.

{| class="wikitable" style="margin: auto;"
!colspan="4"|Interface Performance Summary
|-
!Interface
!Throughput (MS/s @ 16-bit)
!Target
!Recommended Kit
|-
|1 Gigabit
|25 MS/s
|Desktop/Laptop
|[https://www.ettus.com/product/details/1GIGE-KIT SFP Adapter + GigE Cable]
|-
|10 Gigabit
|200 MS/s
|Desktop
|[https://www.ettus.com/product/details/10GIGE-KIT 10 GigE Interface Kit]
|-
|PCI-Express
(PCIe, 4 lane)
|200 MS/S
|Port for a PCIe connection through an MXI Express cable. Can be used to connect an external USRP device.
|[https://www.ni.com/en/contact-us.html Contact Us]
|-

|}

===10 Gigabit Ethernet===
In order to utilize the dual 10 Gigabit Ethernet interfaces, ensure the XG image is installed ([http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_load_fpga_imgs_fpga_flavours see FPGA Image Flavors]). In addition to burning the prerequisite FPGA image, it may also be necessary to tune the network interface card (NIC) to eliminate drops (Ds) and reduce overflows (Os). This is done by increasing the number of RX descriptors ([http://files.ettus.com/manual/page_transport.html#transport_udp_linux see Linux specific notes]).

The <code>benchmark_rate</code> tool can be used to test this capability. Run the following commands to test the X-series USRP over both 10 Gigabit Ethernet interfaces with the maximum rate of 200 Msps per channel:

cd <install-path>/lib/uhd/examples
./benchmark_rate --args="type=x300,addr=<Primary IP>,second_addr=<secondary IP>" --channels="0,1" --rx_rate 200e6

The second interface is specified by the extra argument '''second_addr'''.

'''Recommended 10 Gigabit Ethernet Cards'''
* Intel X520-DA2
** [http://ark.intel.com/products/39776/Intel-Ethernet-Converged-Network-Adapter-X520-DA2 Intel® Ethernet Converged Network Adapter X520-DA2]
* Intel X520-DA1
** [http://ark.intel.com/products/68669/Intel-Ethernet-Converged-Network-Adapter-X520-DA1 Intel® Ethernet Converged Network Adapter X520-DA1 ]
* Intel X710-DA2
** [http://ark.intel.com/products/83964/Intel-Ethernet-Converged-Network-Adapter-X710-DA2 Intel® Ethernet Converged Network Adapter X710-DA2 ]
* Intel X710-DA4
** [http://ark.intel.com/products/83965/Intel-Ethernet-Converged-Network-Adapter-X710-DA4 Intel® Ethernet Converged Network Adapter X710-DA4 ]
* Mellanox MCX4121A-ACAT
** [https://store.mellanox.com/products/mellanox-mcx4121a-acat-connectx-4-lx-en-network-interface-card-25gbe-dual-port-sfp28-pcie3-0-x8-rohs-r6.html Mellanox MCX4121A-ACAT ]

==GPS Disciplined, Oven-Controlled Oscillator (GPSDO)==
The USRP-2794 has a high-accuracy GPS-disciplined oscillator (GPSDO). The GPSDO improves the accuracy of the internal frequency reference to 20 ppb, or 0.1 ppb if the GPS is synchronized to the GPS constellation. When synchronized to the GPS constellation, all USRP™ devices will also be synchronized in time within 50 ns.

* Support GPSDO NMEA Strings
* [http://www.jackson-labs.com/assets/uploads/main/LC_XO_specsheet.pdf JacksonLabs LC_XO]

{| class="wikitable" style="margin: auto;"
|
!Internal TCXO
!GPS-Disciplined Clock
|-
|Frequency Reference
|TCXO
|OCXO
|-
|Frequency Accuracy
|± 2.5ppm
± 2,500 Hz @ 1 GHz
|± 25 ppb
± 25 Hz @ 1 GHz
|-
|Frequency Accuracy
|
|± 0.01ppb
|-
|(GPS-Disciplined)
|
|~ ± 0.01 Hz @ 1 GHz
|-
|GPS Time Sync Accuracy
|
|±50ns to UTC Time**
|-
|10 MHz Reference Phase Drift with GPS Sync
|
|<±20ns After 1 Hour**
|-
|}

===Sensors===
You can query the lock status with the <code>gps_locked</code> sensor, as well as obtain raw NMEA sentences using the <code>gps_gprmc</code>, and <code>gps_gpgga</code> sensors. Location information can be parsed out of the <code>gps_gpgga</code> sensor by using <code>gpsd</code> or another NMEA parser.

==Option: Using the GPIO Expansion Kit==
{|
|style="vertical-align:top; width:60%"|This General Purpose Input/output (GPIO) breakout kit provides access to general purpose digital I/O signals with simple terminal blocks, and a prototyping area where wires and components can be soldered. Each GPIO pin is connected to an FPGA digital line allowing it to be configured as an input, or an output, using the various software frameworks that support the USRP™ GPIO.

These GPIO signals can serve the following functions:

* Control of external devices, such as power amplifiers and RF switches
* Provide output signals that can help with debugging
* Provide observables to be analyzed by oscilloscopes or other external equipment
* Accept input from external devices for local, software-based triggering
* Implement a protocol line such as SPI or I2C
||[[File:Product_x3x0_gpio.jpg|250px]]
|}
===GPIO Expansion Kit Contents===

*1 GPIO Breakout Board
*1 DB-15, 1-meter cable
*GPIO Quick Reference

===Circuit Protection===
The GPIO signals exposed with this breakout kit are routed directly to the USRP device's FPGA with limited protection circuitry. However, the user must take precautionary measures to ensure input/output signals meet the specifications shown in this document. Over voltage, excess current draw, and other conditions can damage the USRP device and void the warranty. Special care should be taken when the USRP is powered off.

===Mounting the GPIO Breakout Board===
The GPIO breakout board can be mounted directly to the DB15 connector of a USRP ™ device, or mounted remotely with the cable provided in this kit. The screws on the DB15 connector of the breakout board must be removed to mount the board directly. For remote mounting, the breakout board is supplied with rubber standoffs to avoid scratching surfaces, and several through-holes for hard mounting with screws or other hardware (not provided).

===Using GPIO with UHD, GNU Radio, and other Third-Party Frameworks===
When used with UHD, or other third party frameworks that leverage UHD, the GPIO expansion can be controlled with simple API calls. For more information, on the C++ API, and examples of how to use the GPIO in frameworks such as GNU Radio, please see the [[Application Notes]] section of the [https://kb.ettus.com Ettus Research Knowledge Base].

===GPIO Specifications (3.3V Bank, LVCMOS)===

{| class="wikitable"
!Parameter
!Typical
|-
!colspan="2"|Configured as Input
|-
|Default Voltage Standard
|3.3V LVCMOS
|-
|Voltage High Threshold
|2.0V
|-
|Voltage Low Threshold
|0.8V
|-
|Voltage Input Limits (no damage)
| -0.3V/3.45V
|-
!colspan="2"|Configured as Output
|-
|Voltage Standard
|3.3V LVCMOS
|-
|Voltage High Output
|2.8V
|-
|Voltage Low Output
|0.4V
|-
|Current Source Capability
|12 mA
|-
|Output Source Impedance
|>33 ohms typical
|-
|}

==Option: Antenna Kit for GPSDO==
The GPSDO Mini Kit will improve the accuracy of the USRP reference clock, even if it does not receive signals from the GPS Constellation. However, to achieve the best accuracy possible, and to achieve global timing alignment across multiple USRPs, Ettus Research recommends the GPSDO Mini Antenna Kit.

==Option: Cables for MIMO Expansion==
Multiple USRP-2974s can be synchronized for coherent operation by sharing a common 10 MHz and 1 PPS signal. We recommend using a star-distribution topology with an OctoClock or OctoClock-G, as seen in Figure 4. This requires matched length cables to be used for both 10 MHz and 1 PPS.

For more information about MIMO operation, please see the MIMO and Synchronization Application Note.
[[File:8mimo.png|700px|center]]
<center>Figure 4 - Star-Distribution of 10 MHz/PPS Signals with OctoClock</center>

==FAQ==

* '''What is the bandwidth of the USRP-2974'''

The ADC rate on each analog RX channel is 200 MS/s quadrature, which provides a theoretical analog bandwidth of approximately 80% of the Nyquist bandwidth of +/- 100 MHz (+/- 80 MHz around the center frequency). The resulting maximum theoretical analog bandwidth is 160 MHz.

FPGA Processing Bandwidth: Up to 200 MS/s quadrature.

Host Bandwidth: Up to 200 MS/s quadrature, dependent on selected interface

For more information about achieving the maximum bandwidth with a USRP-2974, please see the "USRP X300/X310 Configuration Guide" or the "USRP System Bandwidth" application note.

* '''How can I program the USRP-2974'''

Like all other USRP models, the USRP-2974 is compatible with the USRP Hardware Driver™ (UHD) architecture. The UHD architecture is a common driver that allows users to develop and execute applications on the onboard or host computer. UHD provides a direct C++ API to control and stream to/from the USRP-2974. It also provides compatibility with a variety of third-party software frameworks including GNU Radio, LabVIEW, and MATLAB. You may also customize the FPGA image provided with UHD to integrate your own signal processing. For more information about UHD, and supported software frameworks, please see:

http://files.ettus.com/manual/

* '''How do I update the FPGA images and firmware with the latest from UHD'''

You can find more information about updating the FPGA image through PCIe, 1/10 GigE, and JTAG [https://kb.ettus.com/X300/X310_Device_Recovery here].

* '''How can I modify the FPGA of the USRP-2974'''

The source code (Verilog) for the USRP-2794 is available in the UHD repository. The build process leverages the existing CMAKE build system used to compile the host-side driver. A Linux-based setup will provide the best results.

Which FPGA toolchain required to build the FPGA images will depend upon your version of UHD. For more details please see the [https://kb.ettus.com/UHD UHD] Software Resource page.

* '''How much free space is available in the USRP-2974 FPGA'''

Please see the [[#Utilization statistics]] section of this resources page for more information.

* '''What frequency range does the USRP-2974 cover'''

10MHz to 6GHz.

* '''What components do I need to purchase for a complete USRP-2974 system'''

The USRP-2974 is a complete stand alone SDR. Additional components might include RF filters, antennas, RF power amplifiers or other RF components needed for a specific application.

[[Category:Hardware Resources]]

USRP-2974

2025-01-15T18:08:50Z

DylanCaswell: /* Choosing an Interface */

== Device Overview ==
The NI USRP-2974 is a high-performance, USRP software defined radio (SDR) stand-alone device for designing and deploying next generation wireless communications systems. The hardware architecture combines two extended-bandwidth daughterboard slots covering 10 MHz – 6 GHz with up to 160 MHz of baseband bandwidth, multiple high-speed interface options (PCIe, dual 10 GigE), an onboard Intel Core i7 processor, and a large user-programmable Kintex-7 FPGA in a convenient desktop or rack-mountable half-wide 2U form factor.

The USRP-2974 is the equivalent to a USRP X310 with two UBX-160 boards, a GPSDO and an onboard Intel i7 computer. The USRP-2974 comes with NI Linux RTOS pre-installed, but in order to use it with open-source tool-chain, a user will need to install Linux (preferably Fedora or Ubuntu) and then the USRP Hardware driver (UHD). After these have been installed, any other open-source tools can be installed, such as GNU Radio.

== Key Features of the USRP-2974==
{|
|style="vertical-align:top"|
* Intel Core i7 6822EQ 2GHz Quad CoreProcessor
* 16GB DDR4 Memory
* 512GB SSD
* USB-to-UART to the CPU
* Xilinx Kintex-7 XC7K410T FPGA
* 14 bit 200 MS/s ADC
* 16 bit 800 MS/s DAC
* Frequency range: 10 MHz - 6 GHz
* Up 160MHz<sup>*</sup> bandwidth per channel
* 2 Transmit ports
* 2 Receive ports
* GPSDO
* Multiple high-speed interfaces (Dual 10G, PCIe Express, 1G)
|[[File:USRP_2974_frt_dia.jpg|350px|center]]
|}

== Controller - Onboard computer ==
{| class="wikitable"

|System on module (SoM)
|Congatec COM Express conga-TS170
|-

|CPU
|Intel Core i7 6822EQ (2 GHz Quad Core)
|-

|Memory
|SO-DIMM DDR4 16 GB
|-

|SFP+<sup>1</sup>
|10G ETH connection to the SoM
|-

|Cabled PCIe
|PCIe Gen 2 x4
|-

|MicroUSB<sup>2</sup>
|USB-to-UART to the SoM
|-

|RJ45
|1G ETH host connection
|-

|}

<sup>1</sup> Can be bypassed to the FPGA.

<sup>2</sup> Device port for external host.

 
<br>
 

==RF Specifications==

{| class="wikitable"
|-
!colspan="2"|Transmitter
|-
|Number of channels
|2
|-
|Frequency range
|10 MHz to 6 GHz
|-
|Frequency step
|<1kHz
|-
|Maximum output power
|5 mW to 100 mW (7 dBm to 20 dBm)
|-
|Gain range<sup>1</sup>
|0 dB to 31.5 dB
|-
|Gain step
|0.5 dB
|-
|Maximum instantaneous real-time bandwidth
|160 MHz
|-
|}

{| class="wikitable"
|-
!colspan="2"|Receiver
|-
|Number of channels
|2
|-
|Frequency range
|10 MHz to 6 GHz
|-
|Frequency step
|<1 kHz
|-
|Gain range<sup>2</sup>
|0 dB to 37.5 dB
|-
|Gain step
|0.5 dB
|-
|Maximum input power
| -15 dBm
|-
|Noise Figure
|5 dB to 7 dB
|-
|Maximum instantaneous real-time bandwidth<sup>3</sup>
|160MHz                                        
|-
|}
<sup>1</sup> The output power resulting from the gain setting varies over the frequency band and among
devices.

<sup>2</sup>The received signal amplitude resulting from the gain setting varies over the frequency band and
among devices.

<sup>3</sup>The USRP-2974 receiver path has 84 MHz of bandwidth for center frequencies from 10 MHz to
500 MHz

'''NOTE:''' As mentioned earlier, the USRP-2974 incorporates 2 UBX-160 daughterboards. Therefore, for more information on RF performance, please see the [[UBX | UBX hardware resource]] page

==Hardware Specifications==
===USRP Hardware Driver (UHD) version===
* Minimum version of UHD required: '''3.14.1.0'''

===Clocking and Sampling Rates===
There are two master clock rates (MCR) supported on the USRP-2974 like on the X310: 200.0 MHz and 184.32 MHz.

The sampling rate must be an integer decimation rate of the MCR. Ideally, this decimation factor should be an even number. An odd decimation factor will result in additional unwanted attenuation (roll-off from the CIC filter in the DUC and DDC blocks in the FPGA). The valid decimation rates are between 1 and 1024.

For the MCR of 200.0 MHz, the achievable sampling rates using an even decimation factor are 200.0, 100.0, 50.0, 33.33, 25.0, 20.0, 16.67, 14.286 Msps, ... 195.31 Ksps.

For the MCR of 184.32 MHz, the achievable sampling rates using an even decimation factor are 184.32, 92.16, 46.08, 30.72, 23.04, 18.432, 15.36, 13.166 Msps, ... 180.0 Ksps.

If the desired sampling rate is not directly supported by the hardware, then it will be necessary to re-sample in software. This can be done in C++ using libraries such as Liquid DSP [https://github.com/jgaeddert/liquid-dsp], or can be done in GNU Radio, in which there are three blocks that perform sampling rate conversion.

==Physical Specifications==

===Dimensions===
(L × W × H) 29.08 cm × 21.84 cm × 7.98 cm (11.45 in. × 8.60 in. × 3.14 in. )

===Weight===
3.34 kg (7.35 lb)

==Power==
{| class="wikitable"

|Voltage range
|14.25 V to 15.75 V DC
|-

|Current
|10 A, maximum
|-

|Power
|150 W, maximum
|-

|}

==Environmental Specifications==

'''NOTE:''' Indoor use only

===Operating Temperature Range===
* 0 °C to 50 °C

===Maximum altitude===
* 2,000 m (800 mbar) (at 25 °C ambient temperature)

===Operating Humidity Range===
* 10% to 90% non-condensing

===Pollution Degree===
* 2

==System Diagram and Schematics==

===System Block Diagrams===
[[file:2974_blk_dia_hiLevel_v01.png | 800px]]
<center>High Level Block Diagram of the USRP 2974</center>

[[file:2974_blk_dia.png |800px]]

<center>[http://www.ni.com/documentation/en/usrp-software-defined-radio-stand-alone-device/latest/usrp-2974/block-diagram/ Detailed System Block Diagram]</center>

===Schematics===
Because the USRP-2974 is a combination of an Intel i7 SOM and an X310 USRP, a user can reference the X310 Schematics.

[http://files.ettus.com/schematics/x300/x3xx.pdf X310 Schematics]

==Key Component Datasheets==
{| class="wikitable" style="width:80%"
!Part Number
!Description
!Schematic ID (Page)
|-

|[https://www.congatec.com/fileadmin/user_upload/Documents/Datasheets/conga-TS170.pdf conga-TS170]
|System on Module (SoM)
|
|-

|[http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf XC7K410T]
|FPGA
|U23 (3,5,8,9,10,18)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/AD9146.PDF AD9146]
|Dual Channel, 16-Bit, 1230 MSPS DAC
|U12, U36 (7)
|-

|[http://www.ti.com/lit/ds/slas635b/slas635b.pdf ADS62P48]
|Dual Channel, 14-Bit 210 MSPS ADC
|U11, U35 (6)
|-

|[https://www.onsemi.com/pub/Collateral/FIN1002-D.pdf FIN1002]
|High Speed Differential Receiver
|U3, U5, U31, U32 (4)
|-

|[http://ww1.microchip.com/downloads/en/DeviceDoc/20001203U.pdf 24LC256T]
|EEPROM
|U530 (11)
|-

|[http://www.ti.com/lit/ds/symlink/lmk04816.pdf LMK04816BISQ/NOPB_1/3]
|Jitter Cleaner With Dual Loop PLLs
|U531 (11)
|-

|[http://ww1.microchip.com/downloads/en/DeviceDoc/sy89547l.pdf SY89547LMGTR]
|Multiplexer
|U506 (12)
|-

|[http://www.ti.com/lit/ds/symlink/sn74aup1t17.pdf SN74AUP1T17]
|Single Schmitt-Trigger Buffer Gate
|U6, U519 (12)
|-

|[http://www.ti.com/lit/ds/symlink/tps54620.pdf TPS54620RGYT]
|Synchronous Step Down SWIFT™ Converter
|U515 (21); U516 (26)
|-

|[http://cds.linear.com/docs/en/datasheet/1764fb.pdf LT1764EQ-3.3]
|Voltage Regulator
|U27 (21); U516 (26)
|-

|[http://www.ti.com/lit/ds/symlink/tps7a47.pdf TPS7A47]
|Voltage Regulator
|U28, U532 (21)
|-

|[http://cds.linear.com/docs/en/datasheet/3603fc.pdf LTC3603EUF_TRPBF]
|Monolithic Synchronous Step-Down Regulator
|U517 (23); U500 (25); U514, U513 (27)
|-

|[http://www.ti.com/product/TPS77625-EP?keyMatch=TPS77625&tisearch=Search-EN-Everything TPS77625]
|Low-Dropout Voltage Regulators
|U30 (23)
|-

|[http://www.ti.com/lit/ds/symlink/tps79318-ep.pdf TPS79318_SM]
|Low-Dropout Voltage Regulators
|U510 (27)
|-

|[[Media:agile9598503.pdf|OSC-96MHZ-724821-01]]
|Voltage Controlled Crystal Oscillator
|U25 (11)
|-

|}

==FPGA and Baseband==

{| class="wikitable"

|FPGA
|Kintex-7 XC7K410T
|-

|DRAM
|1 GB
|-

|Baseband analog-to-digital converter
(ADC) resolution
|14 bit
|-

|Baseband digital-to-analog converter
(DAC) resolution
|16 bit
|-

|ADC spurious-free dynamic range (sFDR)
|88 dB
|-

|DAC sFDR
|80 dB
|-

|Maximum I/Q sample rate
|200 MS/s
|-

|SFP+<sup>1</sup>
|High speed serial link to one of the FPGA
GTX transceivers
|-

|}

<sup>1</sup>Can be bypassed to the SoM if using the 10 GbE as protocol.

===FPGA User Modifications===

The Verilog code for the FPGA in the NI USRP-2974 is open-source, and users are free to modify and customize it for their needs. However, certain modifications may result in either bricking the device, or even in physical damage to the unit. Specifically, changing the I/O interface of the FPGA in any way (do not remove any of the I/O for the PCIe interface, such as <code>x300_pcie_int</code> and <code>LvFpga_Chinch_Interface</code>), or modifying the pin and timing constraint files, could result in physical damage to other components on the motherboard, external to the FPGA, and doing this will void the warranty. Also, even if the PCIe interface is not being used, you cannot remove or reassign these pins in the constraint file. The constraint files should not be modified. Please note that modifications to the FPGA are made at the risk of the user, and may not be covered by the warranty of the device.

==Interfaces and Connectivity==
Follow the links below for additional information on configuring each interface for the USRP-2974.

*[http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_10gige Dual 10 Gigabit Ethernet] - 200 MS/s Full Duplex @ 16-bit
*[http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_pcie PCIe Express (Desktop)] - 200 MS/s Full Duplex @ 16-bit
*[http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_1gige 1 Gigabit Ethernet] - 25 MS/s Full Duplex @ 16-bit

===Front Panel===

[[File:USRP-2974 Front Panel.jpg|800px]]
[[File:2974_frt_wireframe.png|800px]]

{| class="wikitable"
!Connector
!colspan="2" | '''Use'''
|-
|rowspan="2" | RF 0
|TX1<p>RX1</p>
|Input and output terminal for the RF signal. TX1 RX1 is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input or output channel.
|-
|RX2
|Input terminal for the RF signal. RX2 is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input channel.
|-

|colspan="2" | AUX I/O
|General-purpose I/O (GPIO) port. AUX I/O is controlled by the FPGA.
|-

|rowspan="2" | RF 1
|TX1<p>RX1</p>
|Input and output terminal for the RF signal. TX1 RX1 is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input or output channel.
|-
|RX2
|Input terminal for the RF signal. RX2 is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input channel.
|-

|colspan="2" | DP
|DisplayPort connector to connect one monitor for your controller.
|-

|colspan="2" | USB2.0
|USB ports that support common USB peripheral devices such as flash drives, hard drives, keyboards, and mice.
|-

|colspan="2" | USB3.0
|USB ports that support common USB peripheral devices such as flash drives, hard drives, keyboards, and mice.
|-

|colspan="2" | 1G ETH
|RJ45 port used for 1G ETH connectivity to other ethernet devices.
|-

|colspan="2" | μUSB
|USB port used for UART connectivity to the controller.
|-

|colspan="2" | 1G/10G ETH 0
|SFP+ port used for 10G ETH connectivity to other ethernet devices. Connects to the embedded Linux computer for communication with LabVIEW RT.
|-

|colspan="2" | 1G/10G ETH 1
|SFP+ port used for 1G/10G ETH connectivity to other ethernet devices. Connects to the FPGA. Not currently supported in LabVIEW Communications System Design Suite.
|-

|}

{| class="wikitable"
!colspan="2" | '''LED'''
!'''Description'''
!'''Color'''
!'''State'''
!'''Indication'''
|-
|rowspan="5" | RF 0
|rowspan="3" | TX1<p>RX1</p>
|rowspan="3" | Indicates thetransmit status of the device
|OFF
| —
|The device is not active.
|-
|Red
|Solid
|The device is transmitting data.
|-
|Green
|Solid
|The device is receiving data.
|-
|rowspan="2" | RX2
|rowspan="2" | Indicates the receive status of the device.
|OFF
| —
|The device is not receiving data.
|-
|Green
|Solid
|The device is receiving data.
|-

|rowspan="3" colspan="2"| REF
|rowspan="3" | Indicates the status of the reference signal.
|OFF
| —
|There is no reference signal, or the device is not locked to the reference signal.
|-
|rowspan="2" |Green
|Blinking
|The device is not locked to the reference signal.
|-
|Solid
|The device is locked to the reference signal.
|-

|rowspan="2" colspan="2"| PPS
|rowspan="2" | Indicates the pulse per second (PPS).
|OFF
| —
|There is no PPS timing reference signal, or the device is not locked to the reference signal.
|-
|Green
|Blinking
|The device is locked to the PPS timing reference signal.
|-

|rowspan="2" colspan="2"| GPS
|rowspan="2" | Indicates whether the GPSDO is locked.
|OFF
| —
|There is no GPSDO or the GPSDO is not locked.
|-
|Green
|Solid
|The GPSDO is locked.
|-

|rowspan="5" | RF 1
|rowspan="3" | TX1<p>RX1</p>
|rowspan="3" | Indicates thetransmit status of the device
|OFF
| —
|The device is not active.
|-
|Red
|Solid
|The device is transmitting data.
|-
|Green
|Solid
|The device is receiving data.
|-
|rowspan="2" | RX2
|rowspan="2" | Indicates the receive status of the device.
|OFF
| —
|The device is not receiving data.
|-
|Green
|Solid
|The device is receiving data.
|-

|rowspan="2" colspan="2"| Status
|rowspan="2" | Indicates the status of the device
|OFF
| —
|The device initialized successfully and is ready for use.
|-
|Red
|Blinking
|Hardware error. An internal power supply has failed. Check front-panel I/O connections for shorts. Remove any shorts and cycle power to the USRP-2974. Contact NI if the problem persists.
|-

|rowspan="2" colspan="2"| PWR
|rowspan="2" | Indicates the power status of the device
|OFF
| —
|The device is powered off.
|-
|Green
|Solid
|The devices is powered on.
|-

| rowspan="3" colspan="2" | 10/100/1000
| rowspan="3"| Indicates the speed of the Gigabit Ethernet link.
|OFF
| —
|No link, or 10 Mbps link.
|-
|Green
|Solid
|100 Mbps link.
|-
|Amber
|Solid
|1,000 Mbps link.
|-

| rowspan="3" colspan="2"| ACT/LINK
| rowspan="3" | Indicates the Gigabit Ethernet link activity or status.
|OFF
| —
|No link has been established.
|-
| rowspan="2" | Green
|Solid
|A link has been negotiated.
|-
|Blinking
|Activity on the link.
|-

| rowspan="5" | 1G/10G ETH 0
| rowspan="3" | ACT/LINK
| rowspan="3" | Indicates the status of the SFP+ port.
|OFF
| —
|The link is down.
|-
| rowspan="2" |Green
|Solid
|The link is up.
|-
|Blinking
|The link is active (transmitting and receiving).
|-
| rowspan="2" |10GbE
| rowspan="2" |Indicates the status of the 10G ETH link.
|OFF
| —
|The 10G ETH link is down.
|-
|Green
|Solid
|The 10G ETH link is up.
|-

| rowspan="2" colspan="2" | 1G/10G ETH 1 10GbE
| rowspan="2" | Indicates the status of the 10G ETH link.
|OFF
| —
|The 10G ETH link is down.
|-
|Green
|Solid
|The 10G ETH link is up.
|-

|}

===Rear Panel===
[[File:USRP-2974 Rear Panel.jpg|800px]]
[[File:2974_back_wireframe.png|800px]]

{| class="wikitable"
!Connector
!Use
|-
|REF OUT
|Output terminal for an external reference signal for the LO on the device. REF OUT is an SMA (f) connector with an impedance of 50 Ω, and it is a single-ended reference output. The output signal at this connector is 10 MHz at 3.3 V.
|-

|REF IN
|Input terminal for an external reference signal for the LO on the device. REF IN is an SMA (f) connector with an impedance of 50 Ω, and it is a single-ended reference input. REF IN accepts a 10 MHz signal with a minimum input power of 0 dBm (0.632 Vpk-pk) and a maximum input power of 15 dBm (3.56 Vpk-pk), The optimal signal is a square wave.
|-

|PPS TRIG OUT
|Output terminal for the PPS timing reference. PPS TRIG OUT is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input. The output signal is 0 V to 3.3 V TTL. You can also use this port as a triggered output (TRIG OUT) that you program with the PPS Trig Out I/O signal.
|-

|PPS TRIG IN
|Input terminal for PPS timing reference. PPS TRIG IN is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input channel. PPS TRIG IN accepts 0 V to 3.3 V TTL and 0 V to 5 V TTL signals. You can also use this port as a triggered input (TRIG IN) that you control using NI-USRP software.
|-

|GPS ANT
|Input terminal for the GPS antenna signal. GPS ANT is an SMA (f) connector with a maximum input power of -15 dBm and an output of DC 5 V to power an active antenna. <p> '''Notice:''' Do not terminate the GPS ANT port if you do not use it.
|-

|PCIe x4
|Port for a PCI Express Generation 2, x4 bus connection through an MXI Express four-lane cable. Can be used to connect an external USRP device or external chassis.
|-

|SYSTEM POWER IN
|Input that accepts a 15 V ± 5%, 10 A external DC power connector.
|-

|}

===Ref Clock - 10 MHz===

An external 10 MHz reference clock may be used. The optimal signal is a square wave as created by the [https://kb.ettus.com/OctoClock_CDA-2990 OctoClock/CDDA-2990]. The input signal power level of the reference clock must not exceed +15 dBm.

===PPS - Pulse Per Second===
Using a PPS signal for timestamp synchronization requires a square wave signal with the following a 5Vpp amplitude.

To test the PPS input, you can use the following tool from the UHD examples:

* <code><args></code> are device address arguments (optional if only one USRP device is on your machine)

cd <install-path>/lib/uhd/examples ./test_pps_input –args=<args>

===Front Panel GPIO===
{|
| style="width:50%" |
The GPIO port is not meant to drive big loads. You should not try to source more than 5mA per pin.

The +3.3V is for ESD clamping purposes only and not designed to deliver high currents.

| style="vertical-align:top" | [[File:x3x0 gpio conn.png]]
|}

====Power on state====
The hardware power on state and UHD initial state for the front-panel GPIOs is high-Z. For the X3xx, there are no external pull-ups/pull-downs for the GPIO pins, but the FPGAs do have them and they are configured as follows: X3xx: pull-down.

====Pin Mapping====
* Pin 1: +3.3V
* Pin 2: Data[0]
* Pin 3: Data[1]
* Pin 4: Data[2]
* Pin 5: Data[3]
* Pin 6: Data[4]
* Pin 7: Data[5]
* Pin 8: Data[6]
* Pin 9: Data[7]
* Pin 10: Data[8]
* Pin 11: Data[9]
* Pin 12: Data[10]
* Pin 13: Data[11]
* Pin 14: 0V
* Pin 15: 0V

'''Note''': Please see the [http://files.ettus.com/manual/page_gpio_api.html E3x0/X3x0 GPIO API] for information on configuring and using the GPIO bus.

==Certifications==
===RoHS===
As of December 1st, 2010 all NI/Ettus Research products are RoHS compliant unless otherwise noted. More information can be found at [http://ettus.com/legal/rohs-information http://ettus.com/legal/rohs-information]

===China RoHS===
'''Management Methods for Controlling Pollution Caused by Electronic Information Products Regulation'''

'''Chinese Customers'''

National Instruments is in compliance with the Chinese policy on the Restriction of Hazardous Substances (RoHS) used in Electronic Information Products. For more information about the National Instruments China RoHS compliance, visit [http://www.ni.com/environment/rohs_china ni.com/environment/rohs_china].

==Downloads==
[http://files.ettus.com/manual/md_fpga.html FPGA Resources]

[http://files.ettus.com/binaries/uhd_stable/ UHD Stable Binaries]

[https://github.com/EttusResearch/uhd UHD Source Code on Github]

==Choosing an Interface==

The USRP-2974 provides three interface options – 1 Gigabit Ethernet (1 GigE), 10 Gigabit Ethernet (10 GigE), and PCI-Express (PCIe). The PCIe interface is always available regardless of what FPGA image is loaded. Ettus ships two FPGA image variants, the HG or HGS image which has one 1 GigE interfaces and one 10 GigE interfaces, and the XG image which has two 10 GigE interfaces. Generally, Ettus Research recommends using 10 GigE to achieve the maximum throughput available from the USRP-2974. PCIe is recommended for applications that require the lowest possible latency, which is a desirable characteristic for PHY/MAC research. If your application does not require the full bandwidth of the USRP-2974, the 1 GigE interface serves as a cost-effective fall-back option. Ettus Research provides a complete interface kit for each of these options, which is also shown in the following table.

{| class="wikitable" style="margin: auto;"
!colspan="4"|Interface Performance Summary
|-
!Interface
!Throughput (MS/s @ 16-bit)
!Target
!Recommended Kit
|-
|1 Gigabit
|25 MS/s
|Desktop/Laptop
|[https://www.ettus.com/product/details/1GIGE-KIT SFP Adapter + GigE Cable]
|-
|10 Gigabit
|200 MS/s
|Desktop
|[https://www.ettus.com/product/details/10GIGE-KIT 10 GigE Interface Kit]
|-
|PCI-Express
(PCIe, 4 lane)
|200 MS/S
|Port for a PCIe connection through an MXI Express cable. Can be used to connect an external USRP device.
|[https://www.ni.com/en/contact-us.html Contact Us]
|-

|}

===10 Gigabit Ethernet===
In order to utilize the dual 10 Gigabit Ethernet interfaces, ensure the XG image is installed ([http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_load_fpga_imgs_fpga_flavours see FPGA Image Flavors]). In addition to burning the prerequisite FPGA image, it may also be necessary to tune the network interface card (NIC) to eliminate drops (Ds) and reduce overflows (Os). This is done by increasing the number of RX descriptors ([http://files.ettus.com/manual/page_transport.html#transport_udp_linux see Linux specific notes]).

The <code>benchmark_rate</code> tool can be used to test this capability. Run the following commands to test the X-series USRP over both 10 Gigabit Ethernet interfaces with the maximum rate of 200 Msps per channel:

cd <install-path>/lib/uhd/examples
./benchmark_rate --args="type=x300,addr=<Primary IP>,second_addr=<secondary IP>" --channels="0,1" --rx_rate 200e6

The second interface is specified by the extra argument '''second_addr'''.

'''Recommended 10 Gigabit Ethernet Cards'''
* Intel X520-DA2
** [http://ark.intel.com/products/39776/Intel-Ethernet-Converged-Network-Adapter-X520-DA2 Intel® Ethernet Converged Network Adapter X520-DA2]
* Intel X520-DA1
** [http://ark.intel.com/products/68669/Intel-Ethernet-Converged-Network-Adapter-X520-DA1 Intel® Ethernet Converged Network Adapter X520-DA1 ]
* Intel X710-DA2
** [http://ark.intel.com/products/83964/Intel-Ethernet-Converged-Network-Adapter-X710-DA2 Intel® Ethernet Converged Network Adapter X710-DA2 ]
* Intel X710-DA4
** [http://ark.intel.com/products/83965/Intel-Ethernet-Converged-Network-Adapter-X710-DA4 Intel® Ethernet Converged Network Adapter X710-DA4 ]
* Mellanox MCX4121A-ACAT
** [https://store.mellanox.com/products/mellanox-mcx4121a-acat-connectx-4-lx-en-network-interface-card-25gbe-dual-port-sfp28-pcie3-0-x8-rohs-r6.html Mellanox MCX4121A-ACAT ]

==GPS Disciplined, Oven-Controlled Oscillator (GPSDO)==
The USRP-2794 has a high-accuracy GPS-disciplined oscillator (GPSDO). The GPSDO improves the accuracy of the internal frequency reference to 20 ppb, or 0.1 ppb if the GPS is synchronized to the GPS constellation. When synchronized to the GPS constellation, all USRP™ devices will also be synchronized in time within 50 ns.

* Support GPSDO NMEA Strings
* [http://www.jackson-labs.com/assets/uploads/main/LC_XO_specsheet.pdf JacksonLabs LC_XO]

{| class="wikitable" style="margin: auto;"
|
!Internal TCXO
!GPS-Disciplined Clock
|-
|Frequency Reference
|TCXO
|OCXO
|-
|Frequency Accuracy
|± 2.5ppm
± 2,500 Hz @ 1 GHz
|± 25 ppb
± 25 Hz @ 1 GHz
|-
|Frequency Accuracy
|
|± 0.01ppb
|-
|(GPS-Disciplined)
|
|~ ± 0.01 Hz @ 1 GHz
|-
|GPS Time Sync Accuracy
|
|±50ns to UTC Time**
|-
|10 MHz Reference Phase Drift with GPS Sync
|
|<±20ns After 1 Hour**
|-
|}

===Sensors===
You can query the lock status with the <code>gps_locked</code> sensor, as well as obtain raw NMEA sentences using the <code>gps_gprmc</code>, and <code>gps_gpgga</code> sensors. Location information can be parsed out of the <code>gps_gpgga</code> sensor by using <code>gpsd</code> or another NMEA parser.

==Option: Using the GPIO Expansion Kit==
{|
|style="vertical-align:top; width:60%"|This General Purpose Input/output (GPIO) breakout kit provides access to general purpose digital I/O signals with simple terminal blocks, and a prototyping area where wires and components can be soldered. Each GPIO pin is connected to an FPGA digital line allowing it to be configured as an input, or an output, using the various software frameworks that support the USRP™ GPIO.

These GPIO signals can serve the following functions:

* Control of external devices, such as power amplifiers and RF switches
* Provide output signals that can help with debugging
* Provide observables to be analyzed by oscilloscopes or other external equipment
* Accept input from external devices for local, software-based triggering
* Implement a protocol line such as SPI or I2C
||[[File:Product_x3x0_gpio.jpg|250px]]
|}
===GPIO Expansion Kit Contents===

*1 GPIO Breakout Board
*1 DB-15, 1-meter cable
*GPIO Quick Reference

===Circuit Protection===
The GPIO signals exposed with this breakout kit are routed directly to the USRP device's FPGA with limited protection circuitry. However, the user must take precautionary measures to ensure input/output signals meet the specifications shown in this document. Over voltage, excess current draw, and other conditions can damage the USRP device and void the warranty. Special care should be taken when the USRP is powered off.

===Mounting the GPIO Breakout Board===
The GPIO breakout board can be mounted directly to the DB15 connector of a USRP ™ device, or mounted remotely with the cable provided in this kit. The screws on the DB15 connector of the breakout board must be removed to mount the board directly. For remote mounting, the breakout board is supplied with rubber standoffs to avoid scratching surfaces, and several through-holes for hard mounting with screws or other hardware (not provided).

===Using GPIO with UHD, GNU Radio, and other Third-Party Frameworks===
When used with UHD, or other third party frameworks that leverage UHD, the GPIO expansion can be controlled with simple API calls. For more information, on the C++ API, and examples of how to use the GPIO in frameworks such as GNU Radio, please see the [[Application Notes]] section of the [https://kb.ettus.com Ettus Research Knowledge Base].

===GPIO Specifications (3.3V Bank, LVCMOS)===

{| class="wikitable"
!Parameter
!Typical
|-
!colspan="2"|Configured as Input
|-
|Default Voltage Standard
|3.3V LVCMOS
|-
|Voltage High Threshold
|2.0V
|-
|Voltage Low Threshold
|0.8V
|-
|Voltage Input Limits (no damage)
| -0.3V/3.45V
|-
!colspan="2"|Configured as Output
|-
|Voltage Standard
|3.3V LVCMOS
|-
|Voltage High Output
|2.8V
|-
|Voltage Low Output
|0.4V
|-
|Current Source Capability
|12 mA
|-
|Output Source Impedance
|>33 ohms typical
|-
|}

==Option: Antenna Kit for GPSDO==
The GPSDO Mini Kit will improve the accuracy of the USRP reference clock, even if it does not receive signals from the GPS Constellation. However, to achieve the best accuracy possible, and to achieve global timing alignment across multiple USRPs, Ettus Research recommends the GPSDO Mini Antenna Kit.

==Option: Cables for MIMO Expansion==
Multiple USRP-2974s can be synchronized for coherent operation by sharing a common 10 MHz and 1 PPS signal. We recommend using a star-distribution topology with an OctoClock or OctoClock-G, as seen in Figure 4. This requires matched length cables to be used for both 10 MHz and 1 PPS.

For more information about MIMO operation, please see the MIMO and Synchronization Application Note.
[[File:8mimo.png|700px|center]]
<center>Figure 4 - Star-Distribution of 10 MHz/PPS Signals with OctoClock</center>

==FAQ==

* '''What is the bandwidth of the USRP-2974'''

The ADC rate on each analog RX channel is 200 MS/s quadrature, which provides a theoretical analog bandwidth of approximately 80% of the Nyquist bandwidth of +/- 100 MHz (+/- 80 MHz around the center frequency). The resulting maximum theoretical analog bandwidth is 160 MHz.

FPGA Processing Bandwidth: Up to 200 MS/s quadrature.

Host Bandwidth: Up to 200 MS/s quadrature, dependent on selected interface

For more information about achieving the maximum bandwidth with a USRP-2974, please see the "USRP X300/X310 Configuration Guide" or the "USRP System Bandwidth" application note.

* '''How can I program the USRP-2974'''

Like all other USRP models, the USRP-2974 is compatible with the USRP Hardware Driver™ (UHD) architecture. The UHD architecture is a common driver that allows users to develop and execute applications on the onboard or host computer. UHD provides a direct C++ API to control and stream to/from the USRP-2974. It also provides compatibility with a variety of third-party software frameworks including GNU Radio, LabVIEW, and MATLAB. You may also customize the FPGA image provided with UHD to integrate your own signal processing. For more information about UHD, and supported software frameworks, please see:

http://files.ettus.com/manual/

* '''How do I update the FPGA images and firmware with the latest from UHD'''

You can find more information about updating the FPGA image through PCIe, 1/10 GigE, and JTAG [https://kb.ettus.com/X300/X310_Device_Recovery here].

* '''How can I modify the FPGA of the USRP-2974'''

The source code (Verilog) for the USRP-2794 is available in the UHD repository. The build process leverages the existing CMAKE build system used to compile the host-side driver. A Linux-based setup will provide the best results.

Which FPGA toolchain required to build the FPGA images will depend upon your version of UHD. For more details please see the [https://kb.ettus.com/UHD UHD] Software Resource page.

* '''How much free space is available in the USRP-2974 FPGA'''

Please see the [[#Utilization statistics]] section of this resources page for more information.

* '''What frequency range does the USRP-2974 cover'''

10MHz to 6GHz.

* '''What components do I need to purchase for a complete USRP-2974 system'''

The USRP-2974 is a complete stand alone SDR. Additional components might include RF filters, antennas, RF power amplifiers or other RF components needed for a specific application.

[[Category:Hardware Resources]]

USRP-2974

2025-01-15T17:41:01Z

DylanCaswell: /* Choosing an Interface */

== Device Overview ==
The NI USRP-2974 is a high-performance, USRP software defined radio (SDR) stand-alone device for designing and deploying next generation wireless communications systems. The hardware architecture combines two extended-bandwidth daughterboard slots covering 10 MHz – 6 GHz with up to 160 MHz of baseband bandwidth, multiple high-speed interface options (PCIe, dual 10 GigE), an onboard Intel Core i7 processor, and a large user-programmable Kintex-7 FPGA in a convenient desktop or rack-mountable half-wide 2U form factor.

The USRP-2974 is the equivalent to a USRP X310 with two UBX-160 boards, a GPSDO and an onboard Intel i7 computer. The USRP-2974 comes with NI Linux RTOS pre-installed, but in order to use it with open-source tool-chain, a user will need to install Linux (preferably Fedora or Ubuntu) and then the USRP Hardware driver (UHD). After these have been installed, any other open-source tools can be installed, such as GNU Radio.

== Key Features of the USRP-2974==
{|
|style="vertical-align:top"|
* Intel Core i7 6822EQ 2GHz Quad CoreProcessor
* 16GB DDR4 Memory
* 512GB SSD
* USB-to-UART to the CPU
* Xilinx Kintex-7 XC7K410T FPGA
* 14 bit 200 MS/s ADC
* 16 bit 800 MS/s DAC
* Frequency range: 10 MHz - 6 GHz
* Up 160MHz<sup>*</sup> bandwidth per channel
* 2 Transmit ports
* 2 Receive ports
* GPSDO
* Multiple high-speed interfaces (Dual 10G, PCIe Express, 1G)
|[[File:USRP_2974_frt_dia.jpg|350px|center]]
|}

== Controller - Onboard computer ==
{| class="wikitable"

|System on module (SoM)
|Congatec COM Express conga-TS170
|-

|CPU
|Intel Core i7 6822EQ (2 GHz Quad Core)
|-

|Memory
|SO-DIMM DDR4 16 GB
|-

|SFP+<sup>1</sup>
|10G ETH connection to the SoM
|-

|Cabled PCIe
|PCIe Gen 2 x4
|-

|MicroUSB<sup>2</sup>
|USB-to-UART to the SoM
|-

|RJ45
|1G ETH host connection
|-

|}

<sup>1</sup> Can be bypassed to the FPGA.

<sup>2</sup> Device port for external host.

 
<br>
 

==RF Specifications==

{| class="wikitable"
|-
!colspan="2"|Transmitter
|-
|Number of channels
|2
|-
|Frequency range
|10 MHz to 6 GHz
|-
|Frequency step
|<1kHz
|-
|Maximum output power
|5 mW to 100 mW (7 dBm to 20 dBm)
|-
|Gain range<sup>1</sup>
|0 dB to 31.5 dB
|-
|Gain step
|0.5 dB
|-
|Maximum instantaneous real-time bandwidth
|160 MHz
|-
|}

{| class="wikitable"
|-
!colspan="2"|Receiver
|-
|Number of channels
|2
|-
|Frequency range
|10 MHz to 6 GHz
|-
|Frequency step
|<1 kHz
|-
|Gain range<sup>2</sup>
|0 dB to 37.5 dB
|-
|Gain step
|0.5 dB
|-
|Maximum input power
| -15 dBm
|-
|Noise Figure
|5 dB to 7 dB
|-
|Maximum instantaneous real-time bandwidth<sup>3</sup>
|160MHz                                        
|-
|}
<sup>1</sup> The output power resulting from the gain setting varies over the frequency band and among
devices.

<sup>2</sup>The received signal amplitude resulting from the gain setting varies over the frequency band and
among devices.

<sup>3</sup>The USRP-2974 receiver path has 84 MHz of bandwidth for center frequencies from 10 MHz to
500 MHz

'''NOTE:''' As mentioned earlier, the USRP-2974 incorporates 2 UBX-160 daughterboards. Therefore, for more information on RF performance, please see the [[UBX | UBX hardware resource]] page

==Hardware Specifications==
===USRP Hardware Driver (UHD) version===
* Minimum version of UHD required: '''3.14.1.0'''

===Clocking and Sampling Rates===
There are two master clock rates (MCR) supported on the USRP-2974 like on the X310: 200.0 MHz and 184.32 MHz.

The sampling rate must be an integer decimation rate of the MCR. Ideally, this decimation factor should be an even number. An odd decimation factor will result in additional unwanted attenuation (roll-off from the CIC filter in the DUC and DDC blocks in the FPGA). The valid decimation rates are between 1 and 1024.

For the MCR of 200.0 MHz, the achievable sampling rates using an even decimation factor are 200.0, 100.0, 50.0, 33.33, 25.0, 20.0, 16.67, 14.286 Msps, ... 195.31 Ksps.

For the MCR of 184.32 MHz, the achievable sampling rates using an even decimation factor are 184.32, 92.16, 46.08, 30.72, 23.04, 18.432, 15.36, 13.166 Msps, ... 180.0 Ksps.

If the desired sampling rate is not directly supported by the hardware, then it will be necessary to re-sample in software. This can be done in C++ using libraries such as Liquid DSP [https://github.com/jgaeddert/liquid-dsp], or can be done in GNU Radio, in which there are three blocks that perform sampling rate conversion.

==Physical Specifications==

===Dimensions===
(L × W × H) 29.08 cm × 21.84 cm × 7.98 cm (11.45 in. × 8.60 in. × 3.14 in. )

===Weight===
3.34 kg (7.35 lb)

==Power==
{| class="wikitable"

|Voltage range
|14.25 V to 15.75 V DC
|-

|Current
|10 A, maximum
|-

|Power
|150 W, maximum
|-

|}

==Environmental Specifications==

'''NOTE:''' Indoor use only

===Operating Temperature Range===
* 0 °C to 50 °C

===Maximum altitude===
* 2,000 m (800 mbar) (at 25 °C ambient temperature)

===Operating Humidity Range===
* 10% to 90% non-condensing

===Pollution Degree===
* 2

==System Diagram and Schematics==

===System Block Diagrams===
[[file:2974_blk_dia_hiLevel_v01.png | 800px]]
<center>High Level Block Diagram of the USRP 2974</center>

[[file:2974_blk_dia.png |800px]]

<center>[http://www.ni.com/documentation/en/usrp-software-defined-radio-stand-alone-device/latest/usrp-2974/block-diagram/ Detailed System Block Diagram]</center>

===Schematics===
Because the USRP-2974 is a combination of an Intel i7 SOM and an X310 USRP, a user can reference the X310 Schematics.

[http://files.ettus.com/schematics/x300/x3xx.pdf X310 Schematics]

==Key Component Datasheets==
{| class="wikitable" style="width:80%"
!Part Number
!Description
!Schematic ID (Page)
|-

|[https://www.congatec.com/fileadmin/user_upload/Documents/Datasheets/conga-TS170.pdf conga-TS170]
|System on Module (SoM)
|
|-

|[http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf XC7K410T]
|FPGA
|U23 (3,5,8,9,10,18)
|-

|[http://www.analog.com/media/en/technical-documentation/data-sheets/AD9146.PDF AD9146]
|Dual Channel, 16-Bit, 1230 MSPS DAC
|U12, U36 (7)
|-

|[http://www.ti.com/lit/ds/slas635b/slas635b.pdf ADS62P48]
|Dual Channel, 14-Bit 210 MSPS ADC
|U11, U35 (6)
|-

|[https://www.onsemi.com/pub/Collateral/FIN1002-D.pdf FIN1002]
|High Speed Differential Receiver
|U3, U5, U31, U32 (4)
|-

|[http://ww1.microchip.com/downloads/en/DeviceDoc/20001203U.pdf 24LC256T]
|EEPROM
|U530 (11)
|-

|[http://www.ti.com/lit/ds/symlink/lmk04816.pdf LMK04816BISQ/NOPB_1/3]
|Jitter Cleaner With Dual Loop PLLs
|U531 (11)
|-

|[http://ww1.microchip.com/downloads/en/DeviceDoc/sy89547l.pdf SY89547LMGTR]
|Multiplexer
|U506 (12)
|-

|[http://www.ti.com/lit/ds/symlink/sn74aup1t17.pdf SN74AUP1T17]
|Single Schmitt-Trigger Buffer Gate
|U6, U519 (12)
|-

|[http://www.ti.com/lit/ds/symlink/tps54620.pdf TPS54620RGYT]
|Synchronous Step Down SWIFT™ Converter
|U515 (21); U516 (26)
|-

|[http://cds.linear.com/docs/en/datasheet/1764fb.pdf LT1764EQ-3.3]
|Voltage Regulator
|U27 (21); U516 (26)
|-

|[http://www.ti.com/lit/ds/symlink/tps7a47.pdf TPS7A47]
|Voltage Regulator
|U28, U532 (21)
|-

|[http://cds.linear.com/docs/en/datasheet/3603fc.pdf LTC3603EUF_TRPBF]
|Monolithic Synchronous Step-Down Regulator
|U517 (23); U500 (25); U514, U513 (27)
|-

|[http://www.ti.com/product/TPS77625-EP?keyMatch=TPS77625&tisearch=Search-EN-Everything TPS77625]
|Low-Dropout Voltage Regulators
|U30 (23)
|-

|[http://www.ti.com/lit/ds/symlink/tps79318-ep.pdf TPS79318_SM]
|Low-Dropout Voltage Regulators
|U510 (27)
|-

|[[Media:agile9598503.pdf|OSC-96MHZ-724821-01]]
|Voltage Controlled Crystal Oscillator
|U25 (11)
|-

|}

==FPGA and Baseband==

{| class="wikitable"

|FPGA
|Kintex-7 XC7K410T
|-

|DRAM
|1 GB
|-

|Baseband analog-to-digital converter
(ADC) resolution
|14 bit
|-

|Baseband digital-to-analog converter
(DAC) resolution
|16 bit
|-

|ADC spurious-free dynamic range (sFDR)
|88 dB
|-

|DAC sFDR
|80 dB
|-

|Maximum I/Q sample rate
|200 MS/s
|-

|SFP+<sup>1</sup>
|High speed serial link to one of the FPGA
GTX transceivers
|-

|}

<sup>1</sup>Can be bypassed to the SoM if using the 10 GbE as protocol.

===FPGA User Modifications===

The Verilog code for the FPGA in the NI USRP-2974 is open-source, and users are free to modify and customize it for their needs. However, certain modifications may result in either bricking the device, or even in physical damage to the unit. Specifically, changing the I/O interface of the FPGA in any way (do not remove any of the I/O for the PCIe interface, such as <code>x300_pcie_int</code> and <code>LvFpga_Chinch_Interface</code>), or modifying the pin and timing constraint files, could result in physical damage to other components on the motherboard, external to the FPGA, and doing this will void the warranty. Also, even if the PCIe interface is not being used, you cannot remove or reassign these pins in the constraint file. The constraint files should not be modified. Please note that modifications to the FPGA are made at the risk of the user, and may not be covered by the warranty of the device.

==Interfaces and Connectivity==
Follow the links below for additional information on configuring each interface for the USRP-2974.

*[http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_10gige Dual 10 Gigabit Ethernet] - 200 MS/s Full Duplex @ 16-bit
*[http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_pcie PCIe Express (Desktop)] - 200 MS/s Full Duplex @ 16-bit
*[http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_hw_1gige 1 Gigabit Ethernet] - 25 MS/s Full Duplex @ 16-bit

===Front Panel===

[[File:USRP-2974 Front Panel.jpg|800px]]
[[File:2974_frt_wireframe.png|800px]]

{| class="wikitable"
!Connector
!colspan="2" | '''Use'''
|-
|rowspan="2" | RF 0
|TX1<p>RX1</p>
|Input and output terminal for the RF signal. TX1 RX1 is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input or output channel.
|-
|RX2
|Input terminal for the RF signal. RX2 is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input channel.
|-

|colspan="2" | AUX I/O
|General-purpose I/O (GPIO) port. AUX I/O is controlled by the FPGA.
|-

|rowspan="2" | RF 1
|TX1<p>RX1</p>
|Input and output terminal for the RF signal. TX1 RX1 is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input or output channel.
|-
|RX2
|Input terminal for the RF signal. RX2 is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input channel.
|-

|colspan="2" | DP
|DisplayPort connector to connect one monitor for your controller.
|-

|colspan="2" | USB2.0
|USB ports that support common USB peripheral devices such as flash drives, hard drives, keyboards, and mice.
|-

|colspan="2" | USB3.0
|USB ports that support common USB peripheral devices such as flash drives, hard drives, keyboards, and mice.
|-

|colspan="2" | 1G ETH
|RJ45 port used for 1G ETH connectivity to other ethernet devices.
|-

|colspan="2" | μUSB
|USB port used for UART connectivity to the controller.
|-

|colspan="2" | 1G/10G ETH 0
|SFP+ port used for 10G ETH connectivity to other ethernet devices. Connects to the embedded Linux computer for communication with LabVIEW RT.
|-

|colspan="2" | 1G/10G ETH 1
|SFP+ port used for 1G/10G ETH connectivity to other ethernet devices. Connects to the FPGA. Not currently supported in LabVIEW Communications System Design Suite.
|-

|}

{| class="wikitable"
!colspan="2" | '''LED'''
!'''Description'''
!'''Color'''
!'''State'''
!'''Indication'''
|-
|rowspan="5" | RF 0
|rowspan="3" | TX1<p>RX1</p>
|rowspan="3" | Indicates thetransmit status of the device
|OFF
| —
|The device is not active.
|-
|Red
|Solid
|The device is transmitting data.
|-
|Green
|Solid
|The device is receiving data.
|-
|rowspan="2" | RX2
|rowspan="2" | Indicates the receive status of the device.
|OFF
| —
|The device is not receiving data.
|-
|Green
|Solid
|The device is receiving data.
|-

|rowspan="3" colspan="2"| REF
|rowspan="3" | Indicates the status of the reference signal.
|OFF
| —
|There is no reference signal, or the device is not locked to the reference signal.
|-
|rowspan="2" |Green
|Blinking
|The device is not locked to the reference signal.
|-
|Solid
|The device is locked to the reference signal.
|-

|rowspan="2" colspan="2"| PPS
|rowspan="2" | Indicates the pulse per second (PPS).
|OFF
| —
|There is no PPS timing reference signal, or the device is not locked to the reference signal.
|-
|Green
|Blinking
|The device is locked to the PPS timing reference signal.
|-

|rowspan="2" colspan="2"| GPS
|rowspan="2" | Indicates whether the GPSDO is locked.
|OFF
| —
|There is no GPSDO or the GPSDO is not locked.
|-
|Green
|Solid
|The GPSDO is locked.
|-

|rowspan="5" | RF 1
|rowspan="3" | TX1<p>RX1</p>
|rowspan="3" | Indicates thetransmit status of the device
|OFF
| —
|The device is not active.
|-
|Red
|Solid
|The device is transmitting data.
|-
|Green
|Solid
|The device is receiving data.
|-
|rowspan="2" | RX2
|rowspan="2" | Indicates the receive status of the device.
|OFF
| —
|The device is not receiving data.
|-
|Green
|Solid
|The device is receiving data.
|-

|rowspan="2" colspan="2"| Status
|rowspan="2" | Indicates the status of the device
|OFF
| —
|The device initialized successfully and is ready for use.
|-
|Red
|Blinking
|Hardware error. An internal power supply has failed. Check front-panel I/O connections for shorts. Remove any shorts and cycle power to the USRP-2974. Contact NI if the problem persists.
|-

|rowspan="2" colspan="2"| PWR
|rowspan="2" | Indicates the power status of the device
|OFF
| —
|The device is powered off.
|-
|Green
|Solid
|The devices is powered on.
|-

| rowspan="3" colspan="2" | 10/100/1000
| rowspan="3"| Indicates the speed of the Gigabit Ethernet link.
|OFF
| —
|No link, or 10 Mbps link.
|-
|Green
|Solid
|100 Mbps link.
|-
|Amber
|Solid
|1,000 Mbps link.
|-

| rowspan="3" colspan="2"| ACT/LINK
| rowspan="3" | Indicates the Gigabit Ethernet link activity or status.
|OFF
| —
|No link has been established.
|-
| rowspan="2" | Green
|Solid
|A link has been negotiated.
|-
|Blinking
|Activity on the link.
|-

| rowspan="5" | 1G/10G ETH 0
| rowspan="3" | ACT/LINK
| rowspan="3" | Indicates the status of the SFP+ port.
|OFF
| —
|The link is down.
|-
| rowspan="2" |Green
|Solid
|The link is up.
|-
|Blinking
|The link is active (transmitting and receiving).
|-
| rowspan="2" |10GbE
| rowspan="2" |Indicates the status of the 10G ETH link.
|OFF
| —
|The 10G ETH link is down.
|-
|Green
|Solid
|The 10G ETH link is up.
|-

| rowspan="2" colspan="2" | 1G/10G ETH 1 10GbE
| rowspan="2" | Indicates the status of the 10G ETH link.
|OFF
| —
|The 10G ETH link is down.
|-
|Green
|Solid
|The 10G ETH link is up.
|-

|}

===Rear Panel===
[[File:USRP-2974 Rear Panel.jpg|800px]]
[[File:2974_back_wireframe.png|800px]]

{| class="wikitable"
!Connector
!Use
|-
|REF OUT
|Output terminal for an external reference signal for the LO on the device. REF OUT is an SMA (f) connector with an impedance of 50 Ω, and it is a single-ended reference output. The output signal at this connector is 10 MHz at 3.3 V.
|-

|REF IN
|Input terminal for an external reference signal for the LO on the device. REF IN is an SMA (f) connector with an impedance of 50 Ω, and it is a single-ended reference input. REF IN accepts a 10 MHz signal with a minimum input power of 0 dBm (0.632 Vpk-pk) and a maximum input power of 15 dBm (3.56 Vpk-pk), The optimal signal is a square wave.
|-

|PPS TRIG OUT
|Output terminal for the PPS timing reference. PPS TRIG OUT is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input. The output signal is 0 V to 3.3 V TTL. You can also use this port as a triggered output (TRIG OUT) that you program with the PPS Trig Out I/O signal.
|-

|PPS TRIG IN
|Input terminal for PPS timing reference. PPS TRIG IN is an SMA (f) connector with an impedance of 50 Ω and is a single-ended input channel. PPS TRIG IN accepts 0 V to 3.3 V TTL and 0 V to 5 V TTL signals. You can also use this port as a triggered input (TRIG IN) that you control using NI-USRP software.
|-

|GPS ANT
|Input terminal for the GPS antenna signal. GPS ANT is an SMA (f) connector with a maximum input power of -15 dBm and an output of DC 5 V to power an active antenna. <p> '''Notice:''' Do not terminate the GPS ANT port if you do not use it.
|-

|PCIe x4
|Port for a PCI Express Generation 2, x4 bus connection through an MXI Express four-lane cable. Can be used to connect an external USRP device or external chassis.
|-

|SYSTEM POWER IN
|Input that accepts a 15 V ± 5%, 10 A external DC power connector.
|-

|}

===Ref Clock - 10 MHz===

An external 10 MHz reference clock may be used. The optimal signal is a square wave as created by the [https://kb.ettus.com/OctoClock_CDA-2990 OctoClock/CDDA-2990]. The input signal power level of the reference clock must not exceed +15 dBm.

===PPS - Pulse Per Second===
Using a PPS signal for timestamp synchronization requires a square wave signal with the following a 5Vpp amplitude.

To test the PPS input, you can use the following tool from the UHD examples:

* <code><args></code> are device address arguments (optional if only one USRP device is on your machine)

cd <install-path>/lib/uhd/examples ./test_pps_input –args=<args>

===Front Panel GPIO===
{|
| style="width:50%" |
The GPIO port is not meant to drive big loads. You should not try to source more than 5mA per pin.

The +3.3V is for ESD clamping purposes only and not designed to deliver high currents.

| style="vertical-align:top" | [[File:x3x0 gpio conn.png]]
|}

====Power on state====
The hardware power on state and UHD initial state for the front-panel GPIOs is high-Z. For the X3xx, there are no external pull-ups/pull-downs for the GPIO pins, but the FPGAs do have them and they are configured as follows: X3xx: pull-down.

====Pin Mapping====
* Pin 1: +3.3V
* Pin 2: Data[0]
* Pin 3: Data[1]
* Pin 4: Data[2]
* Pin 5: Data[3]
* Pin 6: Data[4]
* Pin 7: Data[5]
* Pin 8: Data[6]
* Pin 9: Data[7]
* Pin 10: Data[8]
* Pin 11: Data[9]
* Pin 12: Data[10]
* Pin 13: Data[11]
* Pin 14: 0V
* Pin 15: 0V

'''Note''': Please see the [http://files.ettus.com/manual/page_gpio_api.html E3x0/X3x0 GPIO API] for information on configuring and using the GPIO bus.

==Certifications==
===RoHS===
As of December 1st, 2010 all NI/Ettus Research products are RoHS compliant unless otherwise noted. More information can be found at [http://ettus.com/legal/rohs-information http://ettus.com/legal/rohs-information]

===China RoHS===
'''Management Methods for Controlling Pollution Caused by Electronic Information Products Regulation'''

'''Chinese Customers'''

National Instruments is in compliance with the Chinese policy on the Restriction of Hazardous Substances (RoHS) used in Electronic Information Products. For more information about the National Instruments China RoHS compliance, visit [http://www.ni.com/environment/rohs_china ni.com/environment/rohs_china].

==Downloads==
[http://files.ettus.com/manual/md_fpga.html FPGA Resources]

[http://files.ettus.com/binaries/uhd_stable/ UHD Stable Binaries]

[https://github.com/EttusResearch/uhd UHD Source Code on Github]

==Choosing an Interface==

The USRP-2974 provides three interface options – 1 Gigabit Ethernet (1 GigE), 10 Gigabit Ethernet (10 GigE), and PCI-Express (PCIe). The PCIe interface is always available regardless of what FPGA image is loaded. Ettus ships two FPGA image variants, the HG or HGS image which has one 1 GigE interfaces and one 10 GigE interfaces, and the XG image which has two 10 GigE interfaces. Generally, Ettus Research recommends using 10 GigE to achieve the maximum throughput available from the USRP-2974. PCIe is recommended for applications that require the lowest possible latency, which is a desirable characteristic for PHY/MAC research. If your application does not require the full bandwidth of the USRP-2974, the 1 GigE interface serves as a cost-effective fall-back option. Ettus Research provides a complete interface kit for each of these options, which is also shown in the following table.

{| class="wikitable" style="margin: auto;"
!colspan="4"|Interface Performance Summary
|-
!Interface
!Throughput (MS/s @ 16-bit)
!Target
!Recommended Kit
|-
|1 Gigabit
|25 MS/s
|Desktop/Laptop
|[https://www.ettus.com/product/details/1GIGE-KIT SFP Adapter + GigE Cable]
|-
|10 Gigabit
|200 MS/s
|Desktop
|[https://www.ettus.com/product/details/10GIGE-KIT 10 GigE Interface Kit]
|-
|PCI-Express
(PCIe, 4 lane)
|200 MS/S
|Port for a PCI Express Generation 2, x4 bus connection through an MXI Express four-lane cable. Can be used to connect an external USRP device or external chassis.
|[https://www.ni.com/en/contact-us.html Contact Us]
|-

|}

===10 Gigabit Ethernet===
In order to utilize the dual 10 Gigabit Ethernet interfaces, ensure the XG image is installed ([http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_load_fpga_imgs_fpga_flavours see FPGA Image Flavors]). In addition to burning the prerequisite FPGA image, it may also be necessary to tune the network interface card (NIC) to eliminate drops (Ds) and reduce overflows (Os). This is done by increasing the number of RX descriptors ([http://files.ettus.com/manual/page_transport.html#transport_udp_linux see Linux specific notes]).

The <code>benchmark_rate</code> tool can be used to test this capability. Run the following commands to test the X-series USRP over both 10 Gigabit Ethernet interfaces with the maximum rate of 200 Msps per channel:

cd <install-path>/lib/uhd/examples
./benchmark_rate --args="type=x300,addr=<Primary IP>,second_addr=<secondary IP>" --channels="0,1" --rx_rate 200e6

The second interface is specified by the extra argument '''second_addr'''.

'''Recommended 10 Gigabit Ethernet Cards'''
* Intel X520-DA2
** [http://ark.intel.com/products/39776/Intel-Ethernet-Converged-Network-Adapter-X520-DA2 Intel® Ethernet Converged Network Adapter X520-DA2]
* Intel X520-DA1
** [http://ark.intel.com/products/68669/Intel-Ethernet-Converged-Network-Adapter-X520-DA1 Intel® Ethernet Converged Network Adapter X520-DA1 ]
* Intel X710-DA2
** [http://ark.intel.com/products/83964/Intel-Ethernet-Converged-Network-Adapter-X710-DA2 Intel® Ethernet Converged Network Adapter X710-DA2 ]
* Intel X710-DA4
** [http://ark.intel.com/products/83965/Intel-Ethernet-Converged-Network-Adapter-X710-DA4 Intel® Ethernet Converged Network Adapter X710-DA4 ]
* Mellanox MCX4121A-ACAT
** [https://store.mellanox.com/products/mellanox-mcx4121a-acat-connectx-4-lx-en-network-interface-card-25gbe-dual-port-sfp28-pcie3-0-x8-rohs-r6.html Mellanox MCX4121A-ACAT ]

==GPS Disciplined, Oven-Controlled Oscillator (GPSDO)==
The USRP-2794 has a high-accuracy GPS-disciplined oscillator (GPSDO). The GPSDO improves the accuracy of the internal frequency reference to 20 ppb, or 0.1 ppb if the GPS is synchronized to the GPS constellation. When synchronized to the GPS constellation, all USRP™ devices will also be synchronized in time within 50 ns.

* Support GPSDO NMEA Strings
* [http://www.jackson-labs.com/assets/uploads/main/LC_XO_specsheet.pdf JacksonLabs LC_XO]

{| class="wikitable" style="margin: auto;"
|
!Internal TCXO
!GPS-Disciplined Clock
|-
|Frequency Reference
|TCXO
|OCXO
|-
|Frequency Accuracy
|± 2.5ppm
± 2,500 Hz @ 1 GHz
|± 25 ppb
± 25 Hz @ 1 GHz
|-
|Frequency Accuracy
|
|± 0.01ppb
|-
|(GPS-Disciplined)
|
|~ ± 0.01 Hz @ 1 GHz
|-
|GPS Time Sync Accuracy
|
|±50ns to UTC Time**
|-
|10 MHz Reference Phase Drift with GPS Sync
|
|<±20ns After 1 Hour**
|-
|}

===Sensors===
You can query the lock status with the <code>gps_locked</code> sensor, as well as obtain raw NMEA sentences using the <code>gps_gprmc</code>, and <code>gps_gpgga</code> sensors. Location information can be parsed out of the <code>gps_gpgga</code> sensor by using <code>gpsd</code> or another NMEA parser.

==Option: Using the GPIO Expansion Kit==
{|
|style="vertical-align:top; width:60%"|This General Purpose Input/output (GPIO) breakout kit provides access to general purpose digital I/O signals with simple terminal blocks, and a prototyping area where wires and components can be soldered. Each GPIO pin is connected to an FPGA digital line allowing it to be configured as an input, or an output, using the various software frameworks that support the USRP™ GPIO.

These GPIO signals can serve the following functions:

* Control of external devices, such as power amplifiers and RF switches
* Provide output signals that can help with debugging
* Provide observables to be analyzed by oscilloscopes or other external equipment
* Accept input from external devices for local, software-based triggering
* Implement a protocol line such as SPI or I2C
||[[File:Product_x3x0_gpio.jpg|250px]]
|}
===GPIO Expansion Kit Contents===

*1 GPIO Breakout Board
*1 DB-15, 1-meter cable
*GPIO Quick Reference

===Circuit Protection===
The GPIO signals exposed with this breakout kit are routed directly to the USRP device's FPGA with limited protection circuitry. However, the user must take precautionary measures to ensure input/output signals meet the specifications shown in this document. Over voltage, excess current draw, and other conditions can damage the USRP device and void the warranty. Special care should be taken when the USRP is powered off.

===Mounting the GPIO Breakout Board===
The GPIO breakout board can be mounted directly to the DB15 connector of a USRP ™ device, or mounted remotely with the cable provided in this kit. The screws on the DB15 connector of the breakout board must be removed to mount the board directly. For remote mounting, the breakout board is supplied with rubber standoffs to avoid scratching surfaces, and several through-holes for hard mounting with screws or other hardware (not provided).

===Using GPIO with UHD, GNU Radio, and other Third-Party Frameworks===
When used with UHD, or other third party frameworks that leverage UHD, the GPIO expansion can be controlled with simple API calls. For more information, on the C++ API, and examples of how to use the GPIO in frameworks such as GNU Radio, please see the [[Application Notes]] section of the [https://kb.ettus.com Ettus Research Knowledge Base].

===GPIO Specifications (3.3V Bank, LVCMOS)===

{| class="wikitable"
!Parameter
!Typical
|-
!colspan="2"|Configured as Input
|-
|Default Voltage Standard
|3.3V LVCMOS
|-
|Voltage High Threshold
|2.0V
|-
|Voltage Low Threshold
|0.8V
|-
|Voltage Input Limits (no damage)
| -0.3V/3.45V
|-
!colspan="2"|Configured as Output
|-
|Voltage Standard
|3.3V LVCMOS
|-
|Voltage High Output
|2.8V
|-
|Voltage Low Output
|0.4V
|-
|Current Source Capability
|12 mA
|-
|Output Source Impedance
|>33 ohms typical
|-
|}

==Option: Antenna Kit for GPSDO==
The GPSDO Mini Kit will improve the accuracy of the USRP reference clock, even if it does not receive signals from the GPS Constellation. However, to achieve the best accuracy possible, and to achieve global timing alignment across multiple USRPs, Ettus Research recommends the GPSDO Mini Antenna Kit.

==Option: Cables for MIMO Expansion==
Multiple USRP-2974s can be synchronized for coherent operation by sharing a common 10 MHz and 1 PPS signal. We recommend using a star-distribution topology with an OctoClock or OctoClock-G, as seen in Figure 4. This requires matched length cables to be used for both 10 MHz and 1 PPS.

For more information about MIMO operation, please see the MIMO and Synchronization Application Note.
[[File:8mimo.png|700px|center]]
<center>Figure 4 - Star-Distribution of 10 MHz/PPS Signals with OctoClock</center>

==FAQ==

* '''What is the bandwidth of the USRP-2974'''

The ADC rate on each analog RX channel is 200 MS/s quadrature, which provides a theoretical analog bandwidth of approximately 80% of the Nyquist bandwidth of +/- 100 MHz (+/- 80 MHz around the center frequency). The resulting maximum theoretical analog bandwidth is 160 MHz.

FPGA Processing Bandwidth: Up to 200 MS/s quadrature.

Host Bandwidth: Up to 200 MS/s quadrature, dependent on selected interface

For more information about achieving the maximum bandwidth with a USRP-2974, please see the "USRP X300/X310 Configuration Guide" or the "USRP System Bandwidth" application note.

* '''How can I program the USRP-2974'''

Like all other USRP models, the USRP-2974 is compatible with the USRP Hardware Driver™ (UHD) architecture. The UHD architecture is a common driver that allows users to develop and execute applications on the onboard or host computer. UHD provides a direct C++ API to control and stream to/from the USRP-2974. It also provides compatibility with a variety of third-party software frameworks including GNU Radio, LabVIEW, and MATLAB. You may also customize the FPGA image provided with UHD to integrate your own signal processing. For more information about UHD, and supported software frameworks, please see:

http://files.ettus.com/manual/

* '''How do I update the FPGA images and firmware with the latest from UHD'''

You can find more information about updating the FPGA image through PCIe, 1/10 GigE, and JTAG [https://kb.ettus.com/X300/X310_Device_Recovery here].

* '''How can I modify the FPGA of the USRP-2974'''

The source code (Verilog) for the USRP-2794 is available in the UHD repository. The build process leverages the existing CMAKE build system used to compile the host-side driver. A Linux-based setup will provide the best results.

Which FPGA toolchain required to build the FPGA images will depend upon your version of UHD. For more details please see the [https://kb.ettus.com/UHD UHD] Software Resource page.

* '''How much free space is available in the USRP-2974 FPGA'''

Please see the [[#Utilization statistics]] section of this resources page for more information.

* '''What frequency range does the USRP-2974 cover'''

10MHz to 6GHz.

* '''What components do I need to purchase for a complete USRP-2974 system'''

The USRP-2974 is a complete stand alone SDR. Additional components might include RF filters, antennas, RF power amplifiers or other RF components needed for a specific application.

[[Category:Hardware Resources]]

USRP X410/X440 Getting Started Guide

2024-11-13T19:41:44Z

DylanCaswell: /* eMMC Storage */

==Kit Contents==
===X4x0===
{|
|style="vertical-align:top"|
* NI Ettus USRP X410 or X440
* DC Power Supply (12V, 20A)
* 1 Gigabit Ethernet Cat-5e Cable (3m)
* USB-A to USB-C Cable (1m)
* Getting Started Guide URL (QR Code)
* Safety, Environmental, and Regulatory Information
||[[File:X410.jpg|450px|center]]
||[[File:X440.jpg|450px|center]]
|}

==USRP X440 Design Considerations==
* https://kb.ettus.com/About_Sampling_Rates_and_Master_Clock_Rates_for_the_USRP_X440

==You Will Need==
* For Network Mode: A host computer with an available 1 or 10 Gigabit Ethernet interface for sample streaming. In addition to the Ethernet interface used for sampling streaming, your host computer will require a separate 1 Gigabit Ethernet interface for command and control streaming.

* For Stand-Alone Embedded Mode: A host computer with an available 1 Gigabit Ethernet port or a USB 2.0 port to remotely access the embedded Linux operating system running on ARM CPU.

==Proper Care and Handling==

All Ettus Research products are individually tested before shipment. The USRP is guaranteed to be functional at the time it is received by the customer. Improper use or handling of the USRP can cause the device to become non-functional. Take the following precautions to prevent damage to the unit.

* Never allow metal objects to touch the circuit board while powered.
* Always properly terminate the transmit port with an antenna or 50Ω load.
* Always handle the board with proper anti-static methods.
* Never allow the board to directly or indirectly come into contact with any voltage spikes.
* Never allow any water or condensing moisture to come into contact with the device.
* Always use caution with FPGA, firmware, or software modifications.

{|
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |X410: Never apply more than +14 dBm continuous <=3GHz, +17 dBm continuous >3GHz, or +20dBm more than 5 minutes >3GHz of power into any RF input.
|-
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |X440: Never apply more than +13 dBm continuous <=2.5GHz, +17 dBm continuous between 2.5GHz and 3.6 GHz, or +20dBm continuous between 3.6 GHz and 4 GHz of power into any RF input.
|-
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |X410: Always use at least 30dB attenuation if operating in loopback configuration.
|-
|}

==Install and Setup the Software Tools on Your Host Computer==
In order to use your Universal Software Radio Peripheral (USRP™), you must have the software tools correctly installed and configured on your host computer. The easiest way to install USRP Hardware Driver (UHD) is by getting a binary installer package for your operating system as described in the UHD manual about [https://files.ettus.com/manual/page_install.html Binary Installation]. If no binary packages are available for your operating system or you want to modify the sources by yourself, a step-by-step guide is available at the Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on [[Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on Linux|Linux]], [[Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on OS X|OS X]] and [[Building and Installing the USRP Open Source Toolchain (UHD and GNU Radio) on Windows|Windows]] Application Notes.

To find the latest release of UHD, see the UHD repository at https://github.com/EttusResearch/uhd.

The USRP X410 requires UHD version 4.1 or later.
The USRP X440 requires UHD version 4.5 or later.

'''When you receive a brand-new device, it is strongly recommended that you download the latest filesystem image from the Ettus Research website update the unit. It is not recommended that you use the filesystem from the factory as-is. Instructions on downloading the latest filesystem image and updating it is listed below.'''

'''Note that if you are operating the device in Network Mode, the version of UHD running on the host computer and the USRP X4x0 must match.'''

==Assembling the X4x0==
Inside the kit you will find the X4x0 and an X4x0 power supply. Plug these in, connect the 1GbE RJ45 interface to your network, and power on the device by pressing the power button.

==The STM32 Microcontroller==

The STM32 microcontroller (also referred to as the "SCU") controls various low-level features of the X4x0 series motherboard: It controls the power sequencing, reads out fan speeds and some of the temperature sensors. It is connected to the RFSoC via an I2C bus. It is running software based on Chromium EC.

It is possible to log into the STM32 using the serial interface (see Connecting to the Microcontroller). This will allow certain low-level controls, such as remote power cycling should the CPU have become unresponsive for whatever reason.

===Updating the SCU===

The writable SCU image file is stored on the filesystem under /lib/firmware/ni/ec-titanium-revX.RW.bin (where X is a revision compatibility number). To update, simply replace the .bin file with the updated version and reboot.

==eMMC Storage==

The main non-volatile storage of the USRP is an eMMC:

* USRP X410: 16 GB (Module Revision G or earlier) or 32 GB (Module Revision H and later)
* USRP X440: 16 GB (Module Revision D or earlier) or 32 GB (Module Revision E and later)

This storage can be made accessible as a USB Mass Storage device through the USB-OTG connector on the back panel.

The entire root file system (Linux kernel, libraries) and any user data are stored on the eMMC. It is partitioned into four partitions:

Boot partition (contains the bootloader). This partition usually does not require modification.
A data partition, mounted in /data. This is the only partition that is not erased during file system updates.
Two identical system partitions (root file systems). These contain the operating system and the home directory (anything mounted under / that is not the data or boot partition). The reason there are two of these is to enable remote updates: An update running on one partition can update the other one without any effect to the currently running system. Note that the system partitions are erased during updates and are thus unsuitable for permanently storing information.
Note: It is possible to access the currently inactive root file system by mounting it. After logging into the device using serial console or SSH (see the following two sections), run the following commands:

<pre>
$ mkdir temp

$ mount /dev/mmcblk0p3 temp # This assumes mmcblk0p3 is currently not mounted

$ ls temp # You are now accessing the idle partition:

bin data etc lib media proc sbin tmp usr
boot dev home lost+found mnt run sys uboot var
</pre>

The device node in the mount command might differ, depending on which partition is currently already mounted.

==USB Access to eMMC==

While Mender should be used for routine filesystem updates (see Updating Filesystems), it is also possible to access the X4x0's internal eMMC from an external host over USB. This allows accessing or modifying the filesystem, as well as the ability to flash the device with an entirely new filesystem.

In order to do so, you'll need an external computer with two USB ports, and two USB cables to connect the computer to your X4x0. The instructions below assume a Linux host.

First, connect to the APU serial console at a baud rate of 115200. Boot the device, and stop the boot sequence by typing noautoboot at the prompt. Then, run the following command in the U-boot command prompt:

<code>ums 0 mmc 0</code>

This will start the USB mass storage gadget to expose the eMMC as a USB mass storage device. You should see a spinning indicator on the console, which indicates the gadget is active.

Next, connect your external computer to the X4x0's USB to PS port using an OTG cable. Your computer should recognize the X4x0 as a mass storage device, and you should see an entry in your kernel logs (dmesg) that looks like this:

<pre>
usb 3-1: New USB device found, idVendor=3923, idProduct=7a7d, bcdDevice= 2.23
usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 3-1: Product: USB download gadget
usb 3-1: Manufacturer: National Instruments
sd 6:0:0:0: [sdc] 30932992 512-byte logical blocks: (15.8 GB/14.8 GiB)
sdc: sdc1 sdc2 sdc3 sdc4
sd 6:0:0:0: [sdc] Attached SCSI removable disk
</pre>

The exact output will depend on your machine, but from this log you can see that the X4x0 was recognized and /dev/sdc is the block device representing the eMMC, with 4 partitions detected (see eMMC Storage for details on the partition layout).

It is now possible to treat the X4x0's eMMC as you would any other USB drive: the individual partitions can be mounted and accessed, or the entire block device can be read/written.

Once you're finished accessing the device over USB, the u-boot gadget may be stopped by hitting Ctrl-C at the APU serial console.

== Flashing the eMMC ==

Once the X4x0's eMMC is accessible over USB, it's possible to write the filesystem image and thus change the device's filesystem. You can obtain the latest filesystem image by running:

<code>uhd_images_downloader -t sdimg -t x4xx</code>

The output of this command will indicate where the downloaded images were put, or specify a custom location using using the <code>-i INSTALL_LOCATION</code> argument.

There are 2 ways to write the image to the X4x0's eMMC: using <code>dd</code> and <code>bmaptool</code>. Run one of the following commands, replacing <code>/dev/sdX</code> with the block device of the X4x0's eMMC (found in the device's kernel log or by running <code>lsblk</code>). Take care to use the correct block device or else you might overwrite the wrong drive!

<code>sudo dd if=/path/to/usrp_x4xx_fs.sdimg of=/dev/sdX bs=1M</code>

<code>sudo bmaptool copy --bmap /path/to/usrp_x4xx_fs.sdimg.bmap /path/to/usrp_x4xx_fs.sdimg /dev/sdX</code>

The former is generally preferred as it will always work, even if it slower than the latter.

==Using a USRP X4x0 from UHD==
Like any other USRP, all X4x0 USRPs are controlled by the UHD software. To integrate a USRP X4x0 into your C++ application, you would generate a UHD device in the same way you would for any other USRP:

<code>auto usrp = uhd::usrp::multi_usrp::make("type=x4xx");</code>

For a list of which arguments can be passed into make(), see Section Device Arguments.

==Updating Filesystems==

Mender is a third-party software that enables remote updating of the root file system without physically accessing the device (see also the [https://mender.io/ Mender website]). Mender can be executed locally on the device, or a Mender server can be set up which can be used to remotely update an arbitrary number of USRP devices. Mender servers can be self-hosted, or hosted by Mender (see mender.io for pricing and availability).

When updating the file system using Mender, the tool will overwrite the root file system partition that is not currently mounted (note: the onboard flash storage contains two separate root file system partitions, only one is ever used at a single time). Any data stored on that partition will be permanently lost, including the currently loaded FPGA image. After updating that partition, it will reboot into the newly updated partition. Only if the update is confirmed by the user, the update will be made permanent. This means that if an update fails, the device will be always able to reboot into the partition from which the update was originally launched (which presumably is in a working state). Another update can be launched now to correct the previous, failed update, until it works.

To obtain the file system Mender image (these are files with a <code>.mender</code> suffix), run the following command on the host computer with Internet access:

$ sudo uhd_images_downloader -t mender -t x4xx --yes

NOTE: In the output of the command, the folder destination where the images are saved is printed out.

Next, you will need to copy this Mender file system image to the USRP X4xx. This can be done with the Linux utility <code>scp</code>.

$ scp /usr/local/share/uhd/images/usrp_x4xx_fs.mender root@192.168.1.51:~/.

Note: The path and IP may different for your configuration, the command above assumes you're using the default installation path of <code>/usr/local</code> and that the X4xx's IP is <code>192.168.1.51</code>.

After copying the Mender file system image to the X4xx, connect to the X4xx using either the Serial Console, or via SSH to gain shell access.

On the X4xx, run <code>mender install /path/to/latest.mender</code> to update the file system:

$ mender install /home/root/usrp_x4xx_fs.mender

The artifact can also be stored on a remote server:
$ mender install <nowiki>http://server.name/path/to/latest.mender</nowiki>

This procedure will take a few minutes to complete. After mender has logged a successful update, reboot the device:
$ reboot

If the reboot worked, and the device seems functional, commit the changes so that the boot loader knows to permanently boot into this partition:
$ mender -commit

To identify the currently installed Mender artifact from the command line, the following file can be queried on the X4x0:
$ cat /etc/mender/artifact_info

If you are using a Mender server, the updates can be initiated from a web dashboard. From there, you can start the updates without having to log into the device, and you can update groups of USRPs with a few clicks in a web GUI. The dashboard can also be used to inspect the state of USRPs. This is a simple way to update groups of rack-mounted USRPs with custom file systems.

If you are running a hosted server, the updates can be initiated from a web dashboard. From there, you can start the updates without having to log into the device, and can update groups of USRPs with a few clicks in a web GUI. The dashboard can also be used to inspect the state of USRPs. This is a simple way to update groups of rack-mounted USRPs with custom file systems.

==Network Interfaces==
The Ettus USRP X4x0 has various network interfaces:

eth0: RJ45 port.

The RJ45 port comes up with a default configuration of DHCP, that will request a network address from your DHCP server (if available on your network). This interface is agnostic of FPGA image flavor.

int0: internal interface for network communication between the embedded ARM processor and FPGA.

The internal network interface is configured with a static address: 169.254.0.1/24. This interface is agnostic of FPGA image flavor.

sfpX [, sfpX_1, sfpX_2, sfpX_3]: QSFP28 network interface(s), up-to four (one per lane) based on implemented protocol.

Each QSFP28 port has four high-speed transceiver lanes. Therefore, depending on the FPGA image flavor, up-to four different network interfaces may exist per QSFP28 port, using the sfpXfor the first lane, and sfpX_1-3 for the other three lanes. Each network interface has a default static IP address. Note that for multi-lane protocols, such as 100 GbE, a single interface is used (sfpX).
The configuration files for these network interfaces are stored in: <code>/data/network/</code>

{| class="wikitable"
|-
! Interface Name
! Description
! Default Configuration
! Configuration File
! Example: X4_200/X4_400 FPGA image
|-
| eth0
| RJ45
| style="vertical-align:middle; background-color:#FFF;" | DHCP
| style="vertical-align:middle; background-color:#FFF;" | eth0.network
| DHCP
|-
| int0
| Internal
| style="vertical-align:middle; background-color:#FFF;" | 169.254.0.1/24
| style="vertical-align:middle; background-color:#FFF;" | int0.network
| style="vertical-align:middle; background-color:#FFF;" | 169.254.0.1/24
|-
| sfp0
| QSFP28 0 (4-lanes interface or lane 0)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.10.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.10.2/24
|-
| style="background-color:#FFF;" | sfp0_1
| QSFP28 0 (lane 1)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.11.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0_1.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.11.2/24
|-
| style="background-color:#FFF;" | sfp0_2
| QSFP28 0 (lane 2)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.12.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0_2.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.12.2/24
|-
| sfp0_3
| QSFP28 0 (lane 3)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.13.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0_3.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.13.2/24
|-
| sfp1
| QSFP28 1 (4-lanes interface or lane 0)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.20.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
| sfp1_1
| QSFP28 1 (lane 1)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.21.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1_1.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
| style="background-color:#FFF;" | sfp1_2
| QSFP28 1 (lane 2)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.22.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1_2.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
| style="background-color:#FFF;" | sfp1_3
| QSFP28 1 (lane 3)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.23.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1_3.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
|}

==Network Connectivity==
Once the X4x0 has booted, determine the IP address and verify network connectivity by running uhd_find_devices on the host computer:

X410:
<pre>
$ uhd_find_devices

-- UHD Device 0

Device Address:
serial: 1234ABC
addr: 10.2.161.10
claimed: False
mgmt_addr: 10.2.161.10
product: x410
type: x4xx
</pre>

X440:
<pre>
$ uhd_find_devices

-- UHD Device 0

Device Address:
serial: 1234ABC
addr: 10.2.161.10
claimed: False
mgmt_addr: 10.2.161.10
product: x440
type: x4xx
</pre>

By default, an X4x0 will use DHCP to attempt to find an address.

At this point, you should run:

<code>uhd_usrp_probe --args addr=<IP address></code>
to ensure functionality of the device.

Note: If you receive the following error:

<code>Error: RuntimeError: Graph edge list is empty for rx channel 0</code>
then you will need to download a UHD-compatible FPGA as described in Updating the FPGA or using the following command (it assumes that FPGA images have been downloaded previously using uhd_images_downloader, or that the command is run on the device itself):

X410:
<code>uhd_image_loader --args type=x4xx,addr=<ip address>,fpga=X4_200</code>

X440:
<code>uhd_image_loader --args type=x4xx,addr=<ip address>,fpga=X4_400</code>

When running on the device, use <code>127.0.0.1</code> as the IP address.

You can now use existing UHD examples or applications (such as rx_sample_to_file, rx_ascii_art_dft, or tx_waveforms) or other UHD-compatible applications to start receiving and transmitting with the device.

See Network Interfaces for further details on the various network interfaces available on the X4x0.

===Network Status LEDs===
The Ettus USRP X4x0 is equipped with status LEDs for its network-capable ports: RJ45 and QSFP28s, see RJ45 LED Behavior and QSFP28 LED Behavior accordingly.

====RJ45 LED Behavior====
The RJ45 port has two independent LEDs: green (right) and yellow (left). The table below summarizes the LEDs' behavior. Note that link speed indication is not currently supported.

{| class="wikitable"
|- style="font-weight:bold; text-align:center; vertical-align:middle;"
! Link / Activity
! Green LED
! Yellow LED
|-
| style="vertical-align:middle; background-color:#FFF;" | No Link
| Off
| Off
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / No Activity
| On
| Off
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / Activity
| On
| Blinking
|}

====QSFP28 LED Behavior====
Each QSFP28 connector has four LEDs, one for each high-speed transceiver lane. The table below summarizes the LEDs' behavior, note that for multi-lane protocols, such as 100 GbE, the corresponding LEDs are ganged together. Within the same image, multiple speeds on the same port (e.g., both 10 GbE and 100 GbE) are not supported, therefore link speed indication is not supported.

{| class="wikitable"
|- style="font-weight:bold; text-align:center; vertical-align:middle;"
! Link / Activity
! QSFP28 LED (4 Total)
|-
| style="vertical-align:middle; background-color:#FFF;" | No Link
| Off
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / No Activity
| Green (solid)
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / Activity
| Amber (blinking)
|}

==Security-related Settings==
The X4x0 ships without a root password set. It is possible to ssh into the device by simply connecting as root, and thus gaining access to all subsystems. To set a password, run the command

<code>$ passwd</code>
on the device.

==Serial Connection==
It is possible to gain access to the device using a serial terminal emulator. To do so, the USB debug port needs to be connected to a separate computer to gain access. Most Linux, OSX, or other Unix flavors have a tool called 'screen' which can be used for this purpose, by running the following command:

<code>$ sudo screen /dev/ttyUSB2 115200</code>
In this command, we prepend 'sudo' to elevate user privileges (by default, accessing serial ports is not available to regular users), we specify the device node (in this case, /dev/ttyUSB2), and the baud rate (115200).

The exact device node depends on your operating system's driver and other USB devices that might be already connected. Modern Linux systems offer alternatives to simply trying device nodes; instead, the OS might have a directory of symlinks under /dev/serial/by-id:

<pre>$ ls /dev/serial/by-id
usb-Digilent_Digilent_USB_Device_2516351DDCC0-if02-port0
usb-Digilent_Digilent_USB_Device_2516351DDCC0-if03-port0
</pre>

Note: Exact names depend on the host operating system version and may differ.

The first (with the if02 suffix) connects to the STM32 microcontroller (SCU), whereas the second (with the if03 suffix) connects to Linux running on the RFSoC APU.

<code>$ sudo screen /dev/serial/by-id/usb-Digilent_Digilent_USB_Device_2516351DDCC0-if03-port0 115200</code>
After entering the username root (no password is set by default), you should be presented with a shell prompt similar to the following:

<code>root@ni-x4xx-1234ABC:~#</code>
On this prompt, you can enter any Linux command available. Using the default configuration, the serial console will also show all kernel log messages (unlike when using SSH, for example), and give access to the boot loader (U-boot prompt). This can be used to debug kernel or bootloader issues more efficiently than when logged in via SSH.

==Connecting to the Microcontroller==
The microcontroller (which controls the power sequencing, among other things) also has a serial console available. To connect to the microcontroller, use the other UART device. In the example above:

<code>$ sudo screen /dev/serial/by-id/usb-Digilent_Digilent_USB_Device_2516351DDCC0-if02-port0 115200</code>

It provides a very simple prompt. The command 'help' will list all available commands. A direct connection to the microcontroller can be used to hard-reset the device without physically accessing it and other low-level diagnostics. For example, running the command reboot will emulate a reset button press, resetting the state of the device, while the command powerbtn will emulate a power button press, turning the device back on again.

==SSH Connection==
The USRP X4x0 has two network connections: The dual QSFP28 ports, and an RJ45 connector. The latter is by default configured by DHCP; by plugging it into into 1 Gigabit switch on a DHCP-capable network, it will get assigned an IP address and thus be accessible via ssh.

In case your network setup does not include a DHCP server, refer to the section Serial Connection. A serial login can be used to assign an IP address manually.

After the device obtained an IP address you can log in from a Linux or OSX machine by typing:

<code>$ ssh root@ni-x4xx-1234ABC # Replace with your actual device name!</code>
Depending on your network setup, using a .local domain may work:

<code>$ ssh root@ni-x4xx-1234ABC.local</code>
Of course, you can also connect to the IP address directly if you know it (or set it manually using the serial console).

Note: The device's hostname is derived from its serial number by default (<code>ni-x4xx-$SERIAL</code>). You can change the hostname by creating the file <code>/data/network/hostname</code>, saving the desired hostname in it, then rebooting.

On Microsoft Windows, the connection can be established using a tool such as PuTTY, by selecting a username of root without password.

Like with the serial console, you should be presented with a prompt like the following:

<code>root@ni-x4xx-1234ABC:~#</code>

== Autoboot ==

The USRP X4x0 can be configured to power on and boot automatically when power is applied. This setting can be controlled using the <code>eeprom-set-autoboot</code> script. This script is executed directly on the USRP X4x0. To enable autoboot, run <code>eeprom-set-autoboot on</code>; to disable autoboot, run <code>eeprom-set-autoboot off</code>.

==Updating the FPGA==

The FPGA can be updated simply using uhd_image_loader:

<code>uhd_image_loader --args type=x4xx,addr=<IP address of device> --fpga-path <path to .bit></code>
or

<code>uhd_image_loader --args type=x4xx,addr=<IP address of device>,fpga=FPGA_TYPE</code>
A UHD install will likely have pre-built images in /usr/share/uhd/images/. Up-to-date images can be downloaded using the uhd_images_downloader script:

<code>uhd_images_downloader</code>
will download images into /usr/share/uhd/images/ (the path may differ, depending on how UHD was installed).

Also note that the USRP already ships with compatible FPGA images on the device - these images can be loaded by SSH'ing into the device and running:

X410:
<code>uhd_image_loader --args type=x4xx,mgmt_addr=127.0.0.1,fpga=X4_200</code>

X440:
<code>uhd_image_loader --args type=x4xx,mgmt_addr=127.0.0.1,fpga=X4_400</code>

==FPGA Image Flavors==
Unlike the USRP X310 or other third-generation USRP devices, the FPGA image flavors do not only encode how the QSFP28 connectors are configured, but also which master clock rates are available. This is because the data converter configuration is part of the FPGA image (the ADCs/DACs on the X4x0 are on the same die as the FPGA). The image flavors consist of two short strings, separated by an underscore, e.g. X4_200 (X410) or X4_400 (X440) is an image flavor which contains 4x 10 GbE, and can handle an analog bandwidth of 200 MHz or 400 MHz respectively. The first two characters describe the configuration of the QSFP28 ports: 'X' stands for 10 GbE, 'C' stands for 100 GbE. For details see [https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_updating_fpga_types FPGA Image Flavor] in the [https://files.ettus.com/manual USRP Hardware Driver and USRP Manual].

The analog bandwidth determines the available master clock rates.

X410: As of UHD 4.1, only the X4_200 image is shipped with UHD, which allows a 245.76 MHz or 250 MHz master clock rate. With UHD 4.2, the CG_400 image was added allowing for 491.52 MHz and 500 MHz master clock rates. With UHD 4.5, the UC_200 image (245.76 MHz and 250 MHz master clock rate) was added.

X440: As of UHD 4.5, UHD ships with X4_400, X4_1600, CG_400 and CG_1600 images. The X4_400 and CG_400 images allow master clock rates between 125 MHz and 512 MHz and the usage of all 8 channels while the X4_1600 and CG_1600 images allow master clock rates between 125 MHz and 2048 MHz but only the usage of channels 0 and 4.

Any other images are considered experimental (unsupported).

==Device Arguments==

{| class="wikitable" style="vertical-align:middle;"
|- style="font-weight:bold; text-align:center;"
! Key
! Description
! Example Value
|-
| addr
| IPv4 address of primary SFP+ port to connect to.
| addr=192.168.30.2
|-
| second_addr
| IPv4 address of secondary SFP+ port to connect to.
| second_addr=192.168.40.2
|-
| mgmt_addr
| IPv4 address or hostname to which to connect the RPC client. Defaults to `addr'.
| mgmt_addr=ni-sulfur-311FE00
|-
| find_all
| When using broadcast, find all devices, even if unreachable via CHDR.
| find_all=1
|-
| master_clock_rate
| Master Clock Rate in Hz.
| master_clock_rate=250e6
|-
| converter_rate
| Converter Rate in Hz. Only X440 and together with master_clock_rate.
| master_clock_rate=250e6,converter_rate=1000e6
|-
| serialize_init
| Force serial initialization of daughterboards.
| serialize_init=1
|-
| skip_init
| Skip the initialization process for the device.
| skip_init=1
|-
| time_source
| Specify the time (PPS) source.
| time_source=internal
|-
| clock_source
| Specify the reference clock source.
| clock_source=internal
|-
| ref_clk_freq
| Specify the external reference clock frequency, default is 10 MHz.
| ref_clk_freq=20e6
|-
| discovery_port
| Override default value for MPM discovery port.
| discovery_port=49700
|-
| rpc_port
| Override default value for MPM RPC port.
| rpc_port=49701
|}

This is only a subset of the existing device arguments. For a complete list please consult the [https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_usage_args UHD user manual of the X4x0 device series].

==GPS==

The USRP X4x0 includes a Jackson Labs LTE-Lite GPS module. Its antenna port is on the rear panel. When the X4x0 has access to GPS satellite signals, it can use this module to read out the current GPS time and location as well as to discipline an onboard OCXO.

To use the GPS as a clock and time reference, set the device arguments <code>time_source</code> and <code>clock_source</code> to <code>gpsdo</code>.

Note the GPS module is not enabled when the clock source is not set to <code>gpsdo</code>.

Its power-on status can be queried using the <code>gps_enabled</code> GPS sensor. When disabled, none of the sensors will return useful
(if any) values.

Note that acquiring a GPS lock can take some time after enabling the GPS, so if a UHD application is enabling the GPS dynamically, it might take some time before a GPS lock is reported.

To set the clock source and time source dynamically, see the following code:

<pre>
// Set clock/time individually:
usrp->set_clock_source("gpsdo");
usrp->set_time_source("gpsdo");
// This is equivalent to the previous commands, but faster, as it sets
// both settings simultaneously and avoids duplicating settings that are shared
// between these calls.
usrp->set_sync_source("clock_source=gpsdo,time_source=gpsdo");
</pre>

==Front-Panel Programmable GPIOs==

The USRP X4x0 has two HDMI front-panel connectors, which are connected to the FPGA. For a
description of the GPIO control API, see the
[https://files.ettus.com/manual/page_x400_gpio_api.html USRP X4x0 GPIO UHD Manual Entry],
[https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_usage_gpio the USRP X4x0 Series Manual],
the [https://files.ettus.com/manual/page_zbx.html#zbx_atr ZBX ATR section] (X410) and the
[https://files.ettus.com/manual/page_fbx.html#fbx_atr FBX ATR section] (X440).

==Subdev Specifications==

The RF ports on the front panel of the X410 + ZBX correspond to the following subdev specifications:

{| class="wikitable"
|-
! Label
! style="text-align:center; vertical-align:middle; font-weight:bold;" | Subdev Spec
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 0
| A:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 1
| A:1
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 0
| B:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 1
| B:1
|}

The RF ports on the front panel of the X440 + FBX correspond to the following subdev specifications (for xx_400 FPGA images):

{| class="wikitable"
|-
! Label
! style="text-align:center; vertical-align:middle; font-weight:bold;" | Subdev Spec
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 0
| A:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 1
| A:1
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 2
| A:2
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 3
| A:3
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 0
| B:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 1
| B:1
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 2
| B:2
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 3
| B:3
|}

When using a xx_1600 FPGA image on X440, only A:0 and B:0 are available.

The subdev spec slot identifiers "A" and "B" are not reflected on the front panel. They were set to match valid subdev specifications of previous USRPs, maintaining backward compatibility.

These values can be used for uhd::usrp::multi_usrp::set_rx_subdev_spec() and uhd::usrp::multi_usrp::set_tx_subdev_spec() as with other USRPs.

==Rear Panel Status LEDs==

The USRP X4x0 is equipped with four LEDs located on the device's rear panel. Each LED supports four different states: Off, Green, Red, and Amber. One LED (PWR) indicates the device's power state (see Power LED below). The other three LEDs (LED 0, LED 1, and LED 2) are user-configurable, different behaviors are supported for each of these LEDs (see User-configurable LEDs below).

[[File:x4xx_rearpanel_status_leds.png|125px]]

===X4x0 Rear Panel Status LEDs===
Power LED
The USRP X4x0's PWR LED is reserved to visually indicate the user the device's power state. Power LED Behavior describes what each LED state represents.

===Power LED Behavior===

{| class="wikitable" style="background-color:#FFF;"
|- style="font-weight:bold; text-align:center;"
! PWR LED State
! style="vertical-align:middle;" | Meaning
|- style="vertical-align:middle;"
| Off
| No power is applied
|- style="vertical-align:middle;"
| Amber
| Power is good but X4x0 is powered off
|- style="vertical-align:middle;"
| Green
| Power is good and X4x0 is powered on
|- style="vertical-align:middle;"
| Red
| Power error state
|}

===User-configurable LEDs===
The USRP X4x0's user-configurable rear panel status LEDs (LED 0, LED 1, and LED 2) allow the user to have visual indication of various device conditions. Supported LED Behaviors provides a complete list of the supported behaviors for each user-configurable LED. By default, these LEDs are configured as described in LEDs Default Behavior.

The user may alter the default LEDs behavior either temporarily or persistently, see the Temporarily change the LED Behavior or Persistently in the UHD manual to change the LED Behavior accordingly.

https://files.ettus.com/manual/page_usrp_x4xx.html

==Technical Support and Community Knowledge Base==
Technical support for USRP hardware is available through email only. If the product arrived in a nonfunctional state or you require technical assistance, please contact [mailto:support@ettus.com support@ettus.com]. Please allow 24 to 48 hours for response by email, depending on holidays and weekends, although we are often able to reply more quickly than that.

We also recommend that you subscribe to the community mailing lists. The mailing lists have a responsive and knowledgeable community of hundreds of developers and technical users who are located around the world. When you join the community, you will be connected to this group of people who can help you learn about SDR and respond to your technical and specific questions. Often your question can be answered quickly on the mailing lists. Each mailing list also provides an archive of all past conversations and discussions going back many years. Your question or problem may have already been addressed before, and a relevant or helpful solution may already exist in the archive.

Discussions involving the USRP hardware and the UHD software itself are best addressed through the '''usrp-users''' mailing list at [http://usrp-users.ettus.com http://usrp-users.ettus.com].

Discussions involving the use of [http://gnuradio.org/ GNU Radio] with USRP hardware and UHD software are best addressed through the '''discuss-gnuradio''' mailing list at [https://lists.gnu.org/mailman/listinfo/discussgnuradio https://lists.gnu.org/mailman/listinfo/discussgnuradio].

Discussions involving the use of [http://openbts.org/ OpenBTS®] with USRP hardware and UHD software are best addressed through the '''openbts-discuss''' mailing list at [https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss].

The support page on our website is located at [https://www.ettus.com/support https://www.ettus.com/support]. The Knowledge Base is located at [https://kb.ettus.com https://kb.ettus.com].

==Legal Considerations==
Every country has laws governing the transmission and reception of radio signals. Users are solely responsible for insuring they use their USRP system in compliance with all applicable laws and regulations. Before attempting to transmit and/or receive on any frequency, we recommend that you determine what licenses may be required and what restrictions may apply.

*NOTE: This USRP product is a piece of test equipment.

==Sales and Ordering Support==
If you have any non-technical questions related to your order, then please contact us by email at [mailto:orders@ettus.com orders@ettus.com], or by phone at +14086106399 (Monday-Friday, 8 AM - 5 PM, Pacific Time). Please be sure to include your order number and the serial number of your USRP.

==Terms and Conditions of Sale==
Terms and conditions of sale can be accessed online at the following link: http://www.ettus.com/legal/terms-and-conditions-of-sale

[[Category:Getting Started Guides]]
[[Category:X4x0]]

USRP X410/X440 Getting Started Guide

2024-11-12T13:45:20Z

DylanCaswell: /* eMMC Storage */

==Kit Contents==
===X4x0===
{|
|style="vertical-align:top"|
* NI Ettus USRP X410 or X440
* DC Power Supply (12V, 20A)
* 1 Gigabit Ethernet Cat-5e Cable (3m)
* USB-A to USB-C Cable (1m)
* Getting Started Guide URL (QR Code)
* Safety, Environmental, and Regulatory Information
||[[File:X410.jpg|450px|center]]
||[[File:X440.jpg|450px|center]]
|}

==USRP X440 Design Considerations==
* https://kb.ettus.com/About_Sampling_Rates_and_Master_Clock_Rates_for_the_USRP_X440

==You Will Need==
* For Network Mode: A host computer with an available 1 or 10 Gigabit Ethernet interface for sample streaming. In addition to the Ethernet interface used for sampling streaming, your host computer will require a separate 1 Gigabit Ethernet interface for command and control streaming.

* For Stand-Alone Embedded Mode: A host computer with an available 1 Gigabit Ethernet port or a USB 2.0 port to remotely access the embedded Linux operating system running on ARM CPU.

==Proper Care and Handling==

All Ettus Research products are individually tested before shipment. The USRP is guaranteed to be functional at the time it is received by the customer. Improper use or handling of the USRP can cause the device to become non-functional. Take the following precautions to prevent damage to the unit.

* Never allow metal objects to touch the circuit board while powered.
* Always properly terminate the transmit port with an antenna or 50Ω load.
* Always handle the board with proper anti-static methods.
* Never allow the board to directly or indirectly come into contact with any voltage spikes.
* Never allow any water or condensing moisture to come into contact with the device.
* Always use caution with FPGA, firmware, or software modifications.

{|
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |X410: Never apply more than +14 dBm continuous <=3GHz, +17 dBm continuous >3GHz, or +20dBm more than 5 minutes >3GHz of power into any RF input.
|-
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |X440: Never apply more than +13 dBm continuous <=2.5GHz, +17 dBm continuous between 2.5GHz and 3.6 GHz, or +20dBm continuous between 3.6 GHz and 4 GHz of power into any RF input.
|-
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |X410: Always use at least 30dB attenuation if operating in loopback configuration.
|-
|}

==Install and Setup the Software Tools on Your Host Computer==
In order to use your Universal Software Radio Peripheral (USRP™), you must have the software tools correctly installed and configured on your host computer. The easiest way to install USRP Hardware Driver (UHD) is by getting a binary installer package for your operating system as described in the UHD manual about [https://files.ettus.com/manual/page_install.html Binary Installation]. If no binary packages are available for your operating system or you want to modify the sources by yourself, a step-by-step guide is available at the Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on [[Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on Linux|Linux]], [[Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on OS X|OS X]] and [[Building and Installing the USRP Open Source Toolchain (UHD and GNU Radio) on Windows|Windows]] Application Notes.

To find the latest release of UHD, see the UHD repository at https://github.com/EttusResearch/uhd.

The USRP X410 requires UHD version 4.1 or later.
The USRP X440 requires UHD version 4.5 or later.

'''When you receive a brand-new device, it is strongly recommended that you download the latest filesystem image from the Ettus Research website update the unit. It is not recommended that you use the filesystem from the factory as-is. Instructions on downloading the latest filesystem image and updating it is listed below.'''

'''Note that if you are operating the device in Network Mode, the version of UHD running on the host computer and the USRP X4x0 must match.'''

==Assembling the X4x0==
Inside the kit you will find the X4x0 and an X4x0 power supply. Plug these in, connect the 1GbE RJ45 interface to your network, and power on the device by pressing the power button.

==The STM32 Microcontroller==

The STM32 microcontroller (also referred to as the "SCU") controls various low-level features of the X4x0 series motherboard: It controls the power sequencing, reads out fan speeds and some of the temperature sensors. It is connected to the RFSoC via an I2C bus. It is running software based on Chromium EC.

It is possible to log into the STM32 using the serial interface (see Connecting to the Microcontroller). This will allow certain low-level controls, such as remote power cycling should the CPU have become unresponsive for whatever reason.

===Updating the SCU===

The writable SCU image file is stored on the filesystem under /lib/firmware/ni/ec-titanium-revX.RW.bin (where X is a revision compatibility number). To update, simply replace the .bin file with the updated version and reboot.

==eMMC Storage==

The main non-volatile storage of the USRP is 16 GB (Module Revision G or earlier) or 32 GB (Module Revision H onwards) eMMC storage. This storage can be made accessible as a USB Mass Storage device through the USB-OTG connector on the back panel.

The entire root file system (Linux kernel, libraries) and any user data are stored on the eMMC. It is partitioned into four partitions:

Boot partition (contains the bootloader). This partition usually does not require modification.
A data partition, mounted in /data. This is the only partition that is not erased during file system updates.
Two identical system partitions (root file systems). These contain the operating system and the home directory (anything mounted under / that is not the data or boot partition). The reason there are two of these is to enable remote updates: An update running on one partition can update the other one without any effect to the currently running system. Note that the system partitions are erased during updates and are thus unsuitable for permanently storing information.
Note: It is possible to access the currently inactive root file system by mounting it. After logging into the device using serial console or SSH (see the following two sections), run the following commands:

<pre>
$ mkdir temp

$ mount /dev/mmcblk0p3 temp # This assumes mmcblk0p3 is currently not mounted

$ ls temp # You are now accessing the idle partition:

bin data etc lib media proc sbin tmp usr
boot dev home lost+found mnt run sys uboot var
</pre>

The device node in the mount command might differ, depending on which partition is currently already mounted.

==USB Access to eMMC==

While Mender should be used for routine filesystem updates (see Updating Filesystems), it is also possible to access the X4x0's internal eMMC from an external host over USB. This allows accessing or modifying the filesystem, as well as the ability to flash the device with an entirely new filesystem.

In order to do so, you'll need an external computer with two USB ports, and two USB cables to connect the computer to your X4x0. The instructions below assume a Linux host.

First, connect to the APU serial console at a baud rate of 115200. Boot the device, and stop the boot sequence by typing noautoboot at the prompt. Then, run the following command in the U-boot command prompt:

<code>ums 0 mmc 0</code>

This will start the USB mass storage gadget to expose the eMMC as a USB mass storage device. You should see a spinning indicator on the console, which indicates the gadget is active.

Next, connect your external computer to the X4x0's USB to PS port using an OTG cable. Your computer should recognize the X4x0 as a mass storage device, and you should see an entry in your kernel logs (dmesg) that looks like this:

<pre>
usb 3-1: New USB device found, idVendor=3923, idProduct=7a7d, bcdDevice= 2.23
usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 3-1: Product: USB download gadget
usb 3-1: Manufacturer: National Instruments
sd 6:0:0:0: [sdc] 30932992 512-byte logical blocks: (15.8 GB/14.8 GiB)
sdc: sdc1 sdc2 sdc3 sdc4
sd 6:0:0:0: [sdc] Attached SCSI removable disk
</pre>

The exact output will depend on your machine, but from this log you can see that the X4x0 was recognized and /dev/sdc is the block device representing the eMMC, with 4 partitions detected (see eMMC Storage for details on the partition layout).

It is now possible to treat the X4x0's eMMC as you would any other USB drive: the individual partitions can be mounted and accessed, or the entire block device can be read/written.

Once you're finished accessing the device over USB, the u-boot gadget may be stopped by hitting Ctrl-C at the APU serial console.

== Flashing the eMMC ==

Once the X4x0's eMMC is accessible over USB, it's possible to write the filesystem image and thus change the device's filesystem. You can obtain the latest filesystem image by running:

<code>uhd_images_downloader -t sdimg -t x4xx</code>

The output of this command will indicate where the downloaded images were put, or specify a custom location using using the <code>-i INSTALL_LOCATION</code> argument.

There are 2 ways to write the image to the X4x0's eMMC: using <code>dd</code> and <code>bmaptool</code>. Run one of the following commands, replacing <code>/dev/sdX</code> with the block device of the X4x0's eMMC (found in the device's kernel log or by running <code>lsblk</code>). Take care to use the correct block device or else you might overwrite the wrong drive!

<code>sudo dd if=/path/to/usrp_x4xx_fs.sdimg of=/dev/sdX bs=1M</code>

<code>sudo bmaptool copy --bmap /path/to/usrp_x4xx_fs.sdimg.bmap /path/to/usrp_x4xx_fs.sdimg /dev/sdX</code>

The former is generally preferred as it will always work, even if it slower than the latter.

==Using a USRP X4x0 from UHD==
Like any other USRP, all X4x0 USRPs are controlled by the UHD software. To integrate a USRP X4x0 into your C++ application, you would generate a UHD device in the same way you would for any other USRP:

<code>auto usrp = uhd::usrp::multi_usrp::make("type=x4xx");</code>

For a list of which arguments can be passed into make(), see Section Device Arguments.

==Updating Filesystems==

Mender is a third-party software that enables remote updating of the root file system without physically accessing the device (see also the [https://mender.io/ Mender website]). Mender can be executed locally on the device, or a Mender server can be set up which can be used to remotely update an arbitrary number of USRP devices. Mender servers can be self-hosted, or hosted by Mender (see mender.io for pricing and availability).

When updating the file system using Mender, the tool will overwrite the root file system partition that is not currently mounted (note: the onboard flash storage contains two separate root file system partitions, only one is ever used at a single time). Any data stored on that partition will be permanently lost, including the currently loaded FPGA image. After updating that partition, it will reboot into the newly updated partition. Only if the update is confirmed by the user, the update will be made permanent. This means that if an update fails, the device will be always able to reboot into the partition from which the update was originally launched (which presumably is in a working state). Another update can be launched now to correct the previous, failed update, until it works.

To obtain the file system Mender image (these are files with a <code>.mender</code> suffix), run the following command on the host computer with Internet access:

$ sudo uhd_images_downloader -t mender -t x4xx --yes

NOTE: In the output of the command, the folder destination where the images are saved is printed out.

Next, you will need to copy this Mender file system image to the USRP X4xx. This can be done with the Linux utility <code>scp</code>.

$ scp /usr/local/share/uhd/images/usrp_x4xx_fs.mender root@192.168.1.51:~/.

Note: The path and IP may different for your configuration, the command above assumes you're using the default installation path of <code>/usr/local</code> and that the X4xx's IP is <code>192.168.1.51</code>.

After copying the Mender file system image to the X4xx, connect to the X4xx using either the Serial Console, or via SSH to gain shell access.

On the X4xx, run <code>mender install /path/to/latest.mender</code> to update the file system:

$ mender install /home/root/usrp_x4xx_fs.mender

The artifact can also be stored on a remote server:
$ mender install <nowiki>http://server.name/path/to/latest.mender</nowiki>

This procedure will take a few minutes to complete. After mender has logged a successful update, reboot the device:
$ reboot

If the reboot worked, and the device seems functional, commit the changes so that the boot loader knows to permanently boot into this partition:
$ mender -commit

To identify the currently installed Mender artifact from the command line, the following file can be queried on the X4x0:
$ cat /etc/mender/artifact_info

If you are using a Mender server, the updates can be initiated from a web dashboard. From there, you can start the updates without having to log into the device, and you can update groups of USRPs with a few clicks in a web GUI. The dashboard can also be used to inspect the state of USRPs. This is a simple way to update groups of rack-mounted USRPs with custom file systems.

If you are running a hosted server, the updates can be initiated from a web dashboard. From there, you can start the updates without having to log into the device, and can update groups of USRPs with a few clicks in a web GUI. The dashboard can also be used to inspect the state of USRPs. This is a simple way to update groups of rack-mounted USRPs with custom file systems.

==Network Interfaces==
The Ettus USRP X4x0 has various network interfaces:

eth0: RJ45 port.

The RJ45 port comes up with a default configuration of DHCP, that will request a network address from your DHCP server (if available on your network). This interface is agnostic of FPGA image flavor.

int0: internal interface for network communication between the embedded ARM processor and FPGA.

The internal network interface is configured with a static address: 169.254.0.1/24. This interface is agnostic of FPGA image flavor.

sfpX [, sfpX_1, sfpX_2, sfpX_3]: QSFP28 network interface(s), up-to four (one per lane) based on implemented protocol.

Each QSFP28 port has four high-speed transceiver lanes. Therefore, depending on the FPGA image flavor, up-to four different network interfaces may exist per QSFP28 port, using the sfpXfor the first lane, and sfpX_1-3 for the other three lanes. Each network interface has a default static IP address. Note that for multi-lane protocols, such as 100 GbE, a single interface is used (sfpX).
The configuration files for these network interfaces are stored in: <code>/data/network/</code>

{| class="wikitable"
|-
! Interface Name
! Description
! Default Configuration
! Configuration File
! Example: X4_200/X4_400 FPGA image
|-
| eth0
| RJ45
| style="vertical-align:middle; background-color:#FFF;" | DHCP
| style="vertical-align:middle; background-color:#FFF;" | eth0.network
| DHCP
|-
| int0
| Internal
| style="vertical-align:middle; background-color:#FFF;" | 169.254.0.1/24
| style="vertical-align:middle; background-color:#FFF;" | int0.network
| style="vertical-align:middle; background-color:#FFF;" | 169.254.0.1/24
|-
| sfp0
| QSFP28 0 (4-lanes interface or lane 0)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.10.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.10.2/24
|-
| style="background-color:#FFF;" | sfp0_1
| QSFP28 0 (lane 1)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.11.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0_1.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.11.2/24
|-
| style="background-color:#FFF;" | sfp0_2
| QSFP28 0 (lane 2)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.12.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0_2.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.12.2/24
|-
| sfp0_3
| QSFP28 0 (lane 3)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.13.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0_3.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.13.2/24
|-
| sfp1
| QSFP28 1 (4-lanes interface or lane 0)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.20.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
| sfp1_1
| QSFP28 1 (lane 1)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.21.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1_1.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
| style="background-color:#FFF;" | sfp1_2
| QSFP28 1 (lane 2)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.22.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1_2.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
| style="background-color:#FFF;" | sfp1_3
| QSFP28 1 (lane 3)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.23.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1_3.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
|}

==Network Connectivity==
Once the X4x0 has booted, determine the IP address and verify network connectivity by running uhd_find_devices on the host computer:

X410:
<pre>
$ uhd_find_devices

-- UHD Device 0

Device Address:
serial: 1234ABC
addr: 10.2.161.10
claimed: False
mgmt_addr: 10.2.161.10
product: x410
type: x4xx
</pre>

X440:
<pre>
$ uhd_find_devices

-- UHD Device 0

Device Address:
serial: 1234ABC
addr: 10.2.161.10
claimed: False
mgmt_addr: 10.2.161.10
product: x440
type: x4xx
</pre>

By default, an X4x0 will use DHCP to attempt to find an address.

At this point, you should run:

<code>uhd_usrp_probe --args addr=<IP address></code>
to ensure functionality of the device.

Note: If you receive the following error:

<code>Error: RuntimeError: Graph edge list is empty for rx channel 0</code>
then you will need to download a UHD-compatible FPGA as described in Updating the FPGA or using the following command (it assumes that FPGA images have been downloaded previously using uhd_images_downloader, or that the command is run on the device itself):

X410:
<code>uhd_image_loader --args type=x4xx,addr=<ip address>,fpga=X4_200</code>

X440:
<code>uhd_image_loader --args type=x4xx,addr=<ip address>,fpga=X4_400</code>

When running on the device, use <code>127.0.0.1</code> as the IP address.

You can now use existing UHD examples or applications (such as rx_sample_to_file, rx_ascii_art_dft, or tx_waveforms) or other UHD-compatible applications to start receiving and transmitting with the device.

See Network Interfaces for further details on the various network interfaces available on the X4x0.

===Network Status LEDs===
The Ettus USRP X4x0 is equipped with status LEDs for its network-capable ports: RJ45 and QSFP28s, see RJ45 LED Behavior and QSFP28 LED Behavior accordingly.

====RJ45 LED Behavior====
The RJ45 port has two independent LEDs: green (right) and yellow (left). The table below summarizes the LEDs' behavior. Note that link speed indication is not currently supported.

{| class="wikitable"
|- style="font-weight:bold; text-align:center; vertical-align:middle;"
! Link / Activity
! Green LED
! Yellow LED
|-
| style="vertical-align:middle; background-color:#FFF;" | No Link
| Off
| Off
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / No Activity
| On
| Off
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / Activity
| On
| Blinking
|}

====QSFP28 LED Behavior====
Each QSFP28 connector has four LEDs, one for each high-speed transceiver lane. The table below summarizes the LEDs' behavior, note that for multi-lane protocols, such as 100 GbE, the corresponding LEDs are ganged together. Within the same image, multiple speeds on the same port (e.g., both 10 GbE and 100 GbE) are not supported, therefore link speed indication is not supported.

{| class="wikitable"
|- style="font-weight:bold; text-align:center; vertical-align:middle;"
! Link / Activity
! QSFP28 LED (4 Total)
|-
| style="vertical-align:middle; background-color:#FFF;" | No Link
| Off
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / No Activity
| Green (solid)
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / Activity
| Amber (blinking)
|}

==Security-related Settings==
The X4x0 ships without a root password set. It is possible to ssh into the device by simply connecting as root, and thus gaining access to all subsystems. To set a password, run the command

<code>$ passwd</code>
on the device.

==Serial Connection==
It is possible to gain access to the device using a serial terminal emulator. To do so, the USB debug port needs to be connected to a separate computer to gain access. Most Linux, OSX, or other Unix flavors have a tool called 'screen' which can be used for this purpose, by running the following command:

<code>$ sudo screen /dev/ttyUSB2 115200</code>
In this command, we prepend 'sudo' to elevate user privileges (by default, accessing serial ports is not available to regular users), we specify the device node (in this case, /dev/ttyUSB2), and the baud rate (115200).

The exact device node depends on your operating system's driver and other USB devices that might be already connected. Modern Linux systems offer alternatives to simply trying device nodes; instead, the OS might have a directory of symlinks under /dev/serial/by-id:

<pre>$ ls /dev/serial/by-id
usb-Digilent_Digilent_USB_Device_2516351DDCC0-if02-port0
usb-Digilent_Digilent_USB_Device_2516351DDCC0-if03-port0
</pre>

Note: Exact names depend on the host operating system version and may differ.

The first (with the if02 suffix) connects to the STM32 microcontroller (SCU), whereas the second (with the if03 suffix) connects to Linux running on the RFSoC APU.

<code>$ sudo screen /dev/serial/by-id/usb-Digilent_Digilent_USB_Device_2516351DDCC0-if03-port0 115200</code>
After entering the username root (no password is set by default), you should be presented with a shell prompt similar to the following:

<code>root@ni-x4xx-1234ABC:~#</code>
On this prompt, you can enter any Linux command available. Using the default configuration, the serial console will also show all kernel log messages (unlike when using SSH, for example), and give access to the boot loader (U-boot prompt). This can be used to debug kernel or bootloader issues more efficiently than when logged in via SSH.

==Connecting to the Microcontroller==
The microcontroller (which controls the power sequencing, among other things) also has a serial console available. To connect to the microcontroller, use the other UART device. In the example above:

<code>$ sudo screen /dev/serial/by-id/usb-Digilent_Digilent_USB_Device_2516351DDCC0-if02-port0 115200</code>

It provides a very simple prompt. The command 'help' will list all available commands. A direct connection to the microcontroller can be used to hard-reset the device without physically accessing it and other low-level diagnostics. For example, running the command reboot will emulate a reset button press, resetting the state of the device, while the command powerbtn will emulate a power button press, turning the device back on again.

==SSH Connection==
The USRP X4x0 has two network connections: The dual QSFP28 ports, and an RJ45 connector. The latter is by default configured by DHCP; by plugging it into into 1 Gigabit switch on a DHCP-capable network, it will get assigned an IP address and thus be accessible via ssh.

In case your network setup does not include a DHCP server, refer to the section Serial Connection. A serial login can be used to assign an IP address manually.

After the device obtained an IP address you can log in from a Linux or OSX machine by typing:

<code>$ ssh root@ni-x4xx-1234ABC # Replace with your actual device name!</code>
Depending on your network setup, using a .local domain may work:

<code>$ ssh root@ni-x4xx-1234ABC.local</code>
Of course, you can also connect to the IP address directly if you know it (or set it manually using the serial console).

Note: The device's hostname is derived from its serial number by default (<code>ni-x4xx-$SERIAL</code>). You can change the hostname by creating the file <code>/data/network/hostname</code>, saving the desired hostname in it, then rebooting.

On Microsoft Windows, the connection can be established using a tool such as PuTTY, by selecting a username of root without password.

Like with the serial console, you should be presented with a prompt like the following:

<code>root@ni-x4xx-1234ABC:~#</code>

== Autoboot ==

The USRP X4x0 can be configured to power on and boot automatically when power is applied. This setting can be controlled using the <code>eeprom-set-autoboot</code> script. This script is executed directly on the USRP X4x0. To enable autoboot, run <code>eeprom-set-autoboot on</code>; to disable autoboot, run <code>eeprom-set-autoboot off</code>.

==Updating the FPGA==

The FPGA can be updated simply using uhd_image_loader:

<code>uhd_image_loader --args type=x4xx,addr=<IP address of device> --fpga-path <path to .bit></code>
or

<code>uhd_image_loader --args type=x4xx,addr=<IP address of device>,fpga=FPGA_TYPE</code>
A UHD install will likely have pre-built images in /usr/share/uhd/images/. Up-to-date images can be downloaded using the uhd_images_downloader script:

<code>uhd_images_downloader</code>
will download images into /usr/share/uhd/images/ (the path may differ, depending on how UHD was installed).

Also note that the USRP already ships with compatible FPGA images on the device - these images can be loaded by SSH'ing into the device and running:

X410:
<code>uhd_image_loader --args type=x4xx,mgmt_addr=127.0.0.1,fpga=X4_200</code>

X440:
<code>uhd_image_loader --args type=x4xx,mgmt_addr=127.0.0.1,fpga=X4_400</code>

==FPGA Image Flavors==
Unlike the USRP X310 or other third-generation USRP devices, the FPGA image flavors do not only encode how the QSFP28 connectors are configured, but also which master clock rates are available. This is because the data converter configuration is part of the FPGA image (the ADCs/DACs on the X4x0 are on the same die as the FPGA). The image flavors consist of two short strings, separated by an underscore, e.g. X4_200 (X410) or X4_400 (X440) is an image flavor which contains 4x 10 GbE, and can handle an analog bandwidth of 200 MHz or 400 MHz respectively. The first two characters describe the configuration of the QSFP28 ports: 'X' stands for 10 GbE, 'C' stands for 100 GbE. For details see [https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_updating_fpga_types FPGA Image Flavor] in the [https://files.ettus.com/manual USRP Hardware Driver and USRP Manual].

The analog bandwidth determines the available master clock rates.

X410: As of UHD 4.1, only the X4_200 image is shipped with UHD, which allows a 245.76 MHz or 250 MHz master clock rate. With UHD 4.2, the CG_400 image was added allowing for 491.52 MHz and 500 MHz master clock rates. With UHD 4.5, the UC_200 image (245.76 MHz and 250 MHz master clock rate) was added.

X440: As of UHD 4.5, UHD ships with X4_400, X4_1600, CG_400 and CG_1600 images. The X4_400 and CG_400 images allow master clock rates between 125 MHz and 512 MHz and the usage of all 8 channels while the X4_1600 and CG_1600 images allow master clock rates between 125 MHz and 2048 MHz but only the usage of channels 0 and 4.

Any other images are considered experimental (unsupported).

==Device Arguments==

{| class="wikitable" style="vertical-align:middle;"
|- style="font-weight:bold; text-align:center;"
! Key
! Description
! Example Value
|-
| addr
| IPv4 address of primary SFP+ port to connect to.
| addr=192.168.30.2
|-
| second_addr
| IPv4 address of secondary SFP+ port to connect to.
| second_addr=192.168.40.2
|-
| mgmt_addr
| IPv4 address or hostname to which to connect the RPC client. Defaults to `addr'.
| mgmt_addr=ni-sulfur-311FE00
|-
| find_all
| When using broadcast, find all devices, even if unreachable via CHDR.
| find_all=1
|-
| master_clock_rate
| Master Clock Rate in Hz.
| master_clock_rate=250e6
|-
| converter_rate
| Converter Rate in Hz. Only X440 and together with master_clock_rate.
| master_clock_rate=250e6,converter_rate=1000e6
|-
| serialize_init
| Force serial initialization of daughterboards.
| serialize_init=1
|-
| skip_init
| Skip the initialization process for the device.
| skip_init=1
|-
| time_source
| Specify the time (PPS) source.
| time_source=internal
|-
| clock_source
| Specify the reference clock source.
| clock_source=internal
|-
| ref_clk_freq
| Specify the external reference clock frequency, default is 10 MHz.
| ref_clk_freq=20e6
|-
| discovery_port
| Override default value for MPM discovery port.
| discovery_port=49700
|-
| rpc_port
| Override default value for MPM RPC port.
| rpc_port=49701
|}

This is only a subset of the existing device arguments. For a complete list please consult the [https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_usage_args UHD user manual of the X4x0 device series].

==GPS==

The USRP X4x0 includes a Jackson Labs LTE-Lite GPS module. Its antenna port is on the rear panel. When the X4x0 has access to GPS satellite signals, it can use this module to read out the current GPS time and location as well as to discipline an onboard OCXO.

To use the GPS as a clock and time reference, set the device arguments <code>time_source</code> and <code>clock_source</code> to <code>gpsdo</code>.

Note the GPS module is not enabled when the clock source is not set to <code>gpsdo</code>.

Its power-on status can be queried using the <code>gps_enabled</code> GPS sensor. When disabled, none of the sensors will return useful
(if any) values.

Note that acquiring a GPS lock can take some time after enabling the GPS, so if a UHD application is enabling the GPS dynamically, it might take some time before a GPS lock is reported.

To set the clock source and time source dynamically, see the following code:

<pre>
// Set clock/time individually:
usrp->set_clock_source("gpsdo");
usrp->set_time_source("gpsdo");
// This is equivalent to the previous commands, but faster, as it sets
// both settings simultaneously and avoids duplicating settings that are shared
// between these calls.
usrp->set_sync_source("clock_source=gpsdo,time_source=gpsdo");
</pre>

==Front-Panel Programmable GPIOs==

The USRP X4x0 has two HDMI front-panel connectors, which are connected to the FPGA. For a
description of the GPIO control API, see the
[https://files.ettus.com/manual/page_x400_gpio_api.html USRP X4x0 GPIO UHD Manual Entry],
[https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_usage_gpio the USRP X4x0 Series Manual],
the [https://files.ettus.com/manual/page_zbx.html#zbx_atr ZBX ATR section] (X410) and the
[https://files.ettus.com/manual/page_fbx.html#fbx_atr FBX ATR section] (X440).

==Subdev Specifications==

The RF ports on the front panel of the X410 + ZBX correspond to the following subdev specifications:

{| class="wikitable"
|-
! Label
! style="text-align:center; vertical-align:middle; font-weight:bold;" | Subdev Spec
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 0
| A:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 1
| A:1
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 0
| B:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 1
| B:1
|}

The RF ports on the front panel of the X440 + FBX correspond to the following subdev specifications (for xx_400 FPGA images):

{| class="wikitable"
|-
! Label
! style="text-align:center; vertical-align:middle; font-weight:bold;" | Subdev Spec
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 0
| A:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 1
| A:1
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 2
| A:2
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 3
| A:3
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 0
| B:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 1
| B:1
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 2
| B:2
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 3
| B:3
|}

When using a xx_1600 FPGA image on X440, only A:0 and B:0 are available.

The subdev spec slot identifiers "A" and "B" are not reflected on the front panel. They were set to match valid subdev specifications of previous USRPs, maintaining backward compatibility.

These values can be used for uhd::usrp::multi_usrp::set_rx_subdev_spec() and uhd::usrp::multi_usrp::set_tx_subdev_spec() as with other USRPs.

==Rear Panel Status LEDs==

The USRP X4x0 is equipped with four LEDs located on the device's rear panel. Each LED supports four different states: Off, Green, Red, and Amber. One LED (PWR) indicates the device's power state (see Power LED below). The other three LEDs (LED 0, LED 1, and LED 2) are user-configurable, different behaviors are supported for each of these LEDs (see User-configurable LEDs below).

[[File:x4xx_rearpanel_status_leds.png|125px]]

===X4x0 Rear Panel Status LEDs===
Power LED
The USRP X4x0's PWR LED is reserved to visually indicate the user the device's power state. Power LED Behavior describes what each LED state represents.

===Power LED Behavior===

{| class="wikitable" style="background-color:#FFF;"
|- style="font-weight:bold; text-align:center;"
! PWR LED State
! style="vertical-align:middle;" | Meaning
|- style="vertical-align:middle;"
| Off
| No power is applied
|- style="vertical-align:middle;"
| Amber
| Power is good but X4x0 is powered off
|- style="vertical-align:middle;"
| Green
| Power is good and X4x0 is powered on
|- style="vertical-align:middle;"
| Red
| Power error state
|}

===User-configurable LEDs===
The USRP X4x0's user-configurable rear panel status LEDs (LED 0, LED 1, and LED 2) allow the user to have visual indication of various device conditions. Supported LED Behaviors provides a complete list of the supported behaviors for each user-configurable LED. By default, these LEDs are configured as described in LEDs Default Behavior.

The user may alter the default LEDs behavior either temporarily or persistently, see the Temporarily change the LED Behavior or Persistently in the UHD manual to change the LED Behavior accordingly.

https://files.ettus.com/manual/page_usrp_x4xx.html

==Technical Support and Community Knowledge Base==
Technical support for USRP hardware is available through email only. If the product arrived in a nonfunctional state or you require technical assistance, please contact [mailto:support@ettus.com support@ettus.com]. Please allow 24 to 48 hours for response by email, depending on holidays and weekends, although we are often able to reply more quickly than that.

We also recommend that you subscribe to the community mailing lists. The mailing lists have a responsive and knowledgeable community of hundreds of developers and technical users who are located around the world. When you join the community, you will be connected to this group of people who can help you learn about SDR and respond to your technical and specific questions. Often your question can be answered quickly on the mailing lists. Each mailing list also provides an archive of all past conversations and discussions going back many years. Your question or problem may have already been addressed before, and a relevant or helpful solution may already exist in the archive.

Discussions involving the USRP hardware and the UHD software itself are best addressed through the '''usrp-users''' mailing list at [http://usrp-users.ettus.com http://usrp-users.ettus.com].

Discussions involving the use of [http://gnuradio.org/ GNU Radio] with USRP hardware and UHD software are best addressed through the '''discuss-gnuradio''' mailing list at [https://lists.gnu.org/mailman/listinfo/discussgnuradio https://lists.gnu.org/mailman/listinfo/discussgnuradio].

Discussions involving the use of [http://openbts.org/ OpenBTS®] with USRP hardware and UHD software are best addressed through the '''openbts-discuss''' mailing list at [https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss].

The support page on our website is located at [https://www.ettus.com/support https://www.ettus.com/support]. The Knowledge Base is located at [https://kb.ettus.com https://kb.ettus.com].

==Legal Considerations==
Every country has laws governing the transmission and reception of radio signals. Users are solely responsible for insuring they use their USRP system in compliance with all applicable laws and regulations. Before attempting to transmit and/or receive on any frequency, we recommend that you determine what licenses may be required and what restrictions may apply.

*NOTE: This USRP product is a piece of test equipment.

==Sales and Ordering Support==
If you have any non-technical questions related to your order, then please contact us by email at [mailto:orders@ettus.com orders@ettus.com], or by phone at +14086106399 (Monday-Friday, 8 AM - 5 PM, Pacific Time). Please be sure to include your order number and the serial number of your USRP.

==Terms and Conditions of Sale==
Terms and conditions of sale can be accessed online at the following link: http://www.ettus.com/legal/terms-and-conditions-of-sale

[[Category:Getting Started Guides]]
[[Category:X4x0]]

USRP X410/X440 Getting Started Guide

2024-11-05T20:52:59Z

DylanCaswell: /* GPS */

==Kit Contents==
===X4x0===
{|
|style="vertical-align:top"|
* NI Ettus USRP X410 or X440
* DC Power Supply (12V, 20A)
* 1 Gigabit Ethernet Cat-5e Cable (3m)
* USB-A to USB-C Cable (1m)
* Getting Started Guide URL (QR Code)
* Safety, Environmental, and Regulatory Information
||[[File:X410.jpg|450px|center]]
||[[File:X440.jpg|450px|center]]
|}

==USRP X440 Design Considerations==
* https://kb.ettus.com/About_Sampling_Rates_and_Master_Clock_Rates_for_the_USRP_X440

==You Will Need==
* For Network Mode: A host computer with an available 1 or 10 Gigabit Ethernet interface for sample streaming. In addition to the Ethernet interface used for sampling streaming, your host computer will require a separate 1 Gigabit Ethernet interface for command and control streaming.

* For Stand-Alone Embedded Mode: A host computer with an available 1 Gigabit Ethernet port or a USB 2.0 port to remotely access the embedded Linux operating system running on ARM CPU.

==Proper Care and Handling==

All Ettus Research products are individually tested before shipment. The USRP is guaranteed to be functional at the time it is received by the customer. Improper use or handling of the USRP can cause the device to become non-functional. Take the following precautions to prevent damage to the unit.

* Never allow metal objects to touch the circuit board while powered.
* Always properly terminate the transmit port with an antenna or 50Ω load.
* Always handle the board with proper anti-static methods.
* Never allow the board to directly or indirectly come into contact with any voltage spikes.
* Never allow any water or condensing moisture to come into contact with the device.
* Always use caution with FPGA, firmware, or software modifications.

{|
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |X410: Never apply more than +14 dBm continuous <=3GHz, +17 dBm continuous >3GHz, or +20dBm more than 5 minutes >3GHz of power into any RF input.
|-
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |X440: Never apply more than +13 dBm continuous <=2.5GHz, +17 dBm continuous between 2.5GHz and 3.6 GHz, or +20dBm continuous between 3.6 GHz and 4 GHz of power into any RF input.
|-
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |X410: Always use at least 30dB attenuation if operating in loopback configuration.
|-
|}

==Install and Setup the Software Tools on Your Host Computer==
In order to use your Universal Software Radio Peripheral (USRP™), you must have the software tools correctly installed and configured on your host computer. The easiest way to install USRP Hardware Driver (UHD) is by getting a binary installer package for your operating system as described in the UHD manual about [https://files.ettus.com/manual/page_install.html Binary Installation]. If no binary packages are available for your operating system or you want to modify the sources by yourself, a step-by-step guide is available at the Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on [[Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on Linux|Linux]], [[Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on OS X|OS X]] and [[Building and Installing the USRP Open Source Toolchain (UHD and GNU Radio) on Windows|Windows]] Application Notes.

To find the latest release of UHD, see the UHD repository at https://github.com/EttusResearch/uhd.

The USRP X410 requires UHD version 4.1 or later.
The USRP X440 requires UHD version 4.5 or later.

'''When you receive a brand-new device, it is strongly recommended that you download the latest filesystem image from the Ettus Research website update the unit. It is not recommended that you use the filesystem from the factory as-is. Instructions on downloading the latest filesystem image and updating it is listed below.'''

'''Note that if you are operating the device in Network Mode, the version of UHD running on the host computer and the USRP X4x0 must match.'''

==Assembling the X4x0==
Inside the kit you will find the X4x0 and an X4x0 power supply. Plug these in, connect the 1GbE RJ45 interface to your network, and power on the device by pressing the power button.

==The STM32 Microcontroller==

The STM32 microcontroller (also referred to as the "SCU") controls various low-level features of the X4x0 series motherboard: It controls the power sequencing, reads out fan speeds and some of the temperature sensors. It is connected to the RFSoC via an I2C bus. It is running software based on Chromium EC.

It is possible to log into the STM32 using the serial interface (see Connecting to the Microcontroller). This will allow certain low-level controls, such as remote power cycling should the CPU have become unresponsive for whatever reason.

===Updating the SCU===

The writable SCU image file is stored on the filesystem under /lib/firmware/ni/ec-titanium-revX.RW.bin (where X is a revision compatibility number). To update, simply replace the .bin file with the updated version and reboot.

==eMMC Storage==

The main non-volatile storage of the USRP is a 16 GB eMMC storage. This storage can be made accessible as a USB Mass Storage device through the USB-OTG connector on the back panel.

The entire root file system (Linux kernel, libraries) and any user data are stored on the eMMC. It is partitioned into four partitions:

Boot partition (contains the bootloader). This partition usually does not require modification.
A data partition, mounted in /data. This is the only partition that is not erased during file system updates.
Two identical system partitions (root file systems). These contain the operating system and the home directory (anything mounted under / that is not the data or boot partition). The reason there are two of these is to enable remote updates: An update running on one partition can update the other one without any effect to the currently running system. Note that the system partitions are erased during updates and are thus unsuitable for permanently storing information.
Note: It is possible to access the currently inactive root file system by mounting it. After logging into the device using serial console or SSH (see the following two sections), run the following commands:

<pre>
$ mkdir temp

$ mount /dev/mmcblk0p3 temp # This assumes mmcblk0p3 is currently not mounted

$ ls temp # You are now accessing the idle partition:

bin data etc lib media proc sbin tmp usr
boot dev home lost+found mnt run sys uboot var
</pre>

The device node in the mount command might differ, depending on which partition is currently already mounted.

==USB Access to eMMC==

While Mender should be used for routine filesystem updates (see Updating Filesystems), it is also possible to access the X4x0's internal eMMC from an external host over USB. This allows accessing or modifying the filesystem, as well as the ability to flash the device with an entirely new filesystem.

In order to do so, you'll need an external computer with two USB ports, and two USB cables to connect the computer to your X4x0. The instructions below assume a Linux host.

First, connect to the APU serial console at a baud rate of 115200. Boot the device, and stop the boot sequence by typing noautoboot at the prompt. Then, run the following command in the U-boot command prompt:

<code>ums 0 mmc 0</code>

This will start the USB mass storage gadget to expose the eMMC as a USB mass storage device. You should see a spinning indicator on the console, which indicates the gadget is active.

Next, connect your external computer to the X4x0's USB to PS port using an OTG cable. Your computer should recognize the X4x0 as a mass storage device, and you should see an entry in your kernel logs (dmesg) that looks like this:

<pre>
usb 3-1: New USB device found, idVendor=3923, idProduct=7a7d, bcdDevice= 2.23
usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 3-1: Product: USB download gadget
usb 3-1: Manufacturer: National Instruments
sd 6:0:0:0: [sdc] 30932992 512-byte logical blocks: (15.8 GB/14.8 GiB)
sdc: sdc1 sdc2 sdc3 sdc4
sd 6:0:0:0: [sdc] Attached SCSI removable disk
</pre>

The exact output will depend on your machine, but from this log you can see that the X4x0 was recognized and /dev/sdc is the block device representing the eMMC, with 4 partitions detected (see eMMC Storage for details on the partition layout).

It is now possible to treat the X4x0's eMMC as you would any other USB drive: the individual partitions can be mounted and accessed, or the entire block device can be read/written.

Once you're finished accessing the device over USB, the u-boot gadget may be stopped by hitting Ctrl-C at the APU serial console.

== Flashing the eMMC ==

Once the X4x0's eMMC is accessible over USB, it's possible to write the filesystem image and thus change the device's filesystem. You can obtain the latest filesystem image by running:

<code>uhd_images_downloader -t sdimg -t x4xx</code>

The output of this command will indicate where the downloaded images were put, or specify a custom location using using the <code>-i INSTALL_LOCATION</code> argument.

There are 2 ways to write the image to the X4x0's eMMC: using <code>dd</code> and <code>bmaptool</code>. Run one of the following commands, replacing <code>/dev/sdX</code> with the block device of the X4x0's eMMC (found in the device's kernel log or by running <code>lsblk</code>). Take care to use the correct block device or else you might overwrite the wrong drive!

<code>sudo dd if=/path/to/usrp_x4xx_fs.sdimg of=/dev/sdX bs=1M</code>

<code>sudo bmaptool copy --bmap /path/to/usrp_x4xx_fs.sdimg.bmap /path/to/usrp_x4xx_fs.sdimg /dev/sdX</code>

The former is generally preferred as it will always work, even if it slower than the latter.

==Using a USRP X4x0 from UHD==
Like any other USRP, all X4x0 USRPs are controlled by the UHD software. To integrate a USRP X4x0 into your C++ application, you would generate a UHD device in the same way you would for any other USRP:

<code>auto usrp = uhd::usrp::multi_usrp::make("type=x4xx");</code>

For a list of which arguments can be passed into make(), see Section Device Arguments.

==Updating Filesystems==

Mender is a third-party software that enables remote updating of the root file system without physically accessing the device (see also the [https://mender.io/ Mender website]). Mender can be executed locally on the device, or a Mender server can be set up which can be used to remotely update an arbitrary number of USRP devices. Mender servers can be self-hosted, or hosted by Mender (see mender.io for pricing and availability).

When updating the file system using Mender, the tool will overwrite the root file system partition that is not currently mounted (note: the onboard flash storage contains two separate root file system partitions, only one is ever used at a single time). Any data stored on that partition will be permanently lost, including the currently loaded FPGA image. After updating that partition, it will reboot into the newly updated partition. Only if the update is confirmed by the user, the update will be made permanent. This means that if an update fails, the device will be always able to reboot into the partition from which the update was originally launched (which presumably is in a working state). Another update can be launched now to correct the previous, failed update, until it works.

To obtain the file system Mender image (these are files with a <code>.mender</code> suffix), run the following command on the host computer with Internet access:

$ sudo uhd_images_downloader -t mender -t x4xx --yes

NOTE: In the output of the command, the folder destination where the images are saved is printed out.

Next, you will need to copy this Mender file system image to the USRP X4xx. This can be done with the Linux utility <code>scp</code>.

$ scp /usr/local/share/uhd/images/usrp_x4xx_fs.mender root@192.168.1.51:~/.

Note: The path and IP may different for your configuration, the command above assumes you're using the default installation path of <code>/usr/local</code> and that the X4xx's IP is <code>192.168.1.51</code>.

After copying the Mender file system image to the X4xx, connect to the X4xx using either the Serial Console, or via SSH to gain shell access.

On the X4xx, run <code>mender install /path/to/latest.mender</code> to update the file system:

$ mender install /home/root/usrp_x4xx_fs.mender

The artifact can also be stored on a remote server:
$ mender install <nowiki>http://server.name/path/to/latest.mender</nowiki>

This procedure will take a few minutes to complete. After mender has logged a successful update, reboot the device:
$ reboot

If the reboot worked, and the device seems functional, commit the changes so that the boot loader knows to permanently boot into this partition:
$ mender -commit

To identify the currently installed Mender artifact from the command line, the following file can be queried on the X4x0:
$ cat /etc/mender/artifact_info

If you are using a Mender server, the updates can be initiated from a web dashboard. From there, you can start the updates without having to log into the device, and you can update groups of USRPs with a few clicks in a web GUI. The dashboard can also be used to inspect the state of USRPs. This is a simple way to update groups of rack-mounted USRPs with custom file systems.

If you are running a hosted server, the updates can be initiated from a web dashboard. From there, you can start the updates without having to log into the device, and can update groups of USRPs with a few clicks in a web GUI. The dashboard can also be used to inspect the state of USRPs. This is a simple way to update groups of rack-mounted USRPs with custom file systems.

==Network Interfaces==
The Ettus USRP X4x0 has various network interfaces:

eth0: RJ45 port.

The RJ45 port comes up with a default configuration of DHCP, that will request a network address from your DHCP server (if available on your network). This interface is agnostic of FPGA image flavor.

int0: internal interface for network communication between the embedded ARM processor and FPGA.

The internal network interface is configured with a static address: 169.254.0.1/24. This interface is agnostic of FPGA image flavor.

sfpX [, sfpX_1, sfpX_2, sfpX_3]: QSFP28 network interface(s), up-to four (one per lane) based on implemented protocol.

Each QSFP28 port has four high-speed transceiver lanes. Therefore, depending on the FPGA image flavor, up-to four different network interfaces may exist per QSFP28 port, using the sfpXfor the first lane, and sfpX_1-3 for the other three lanes. Each network interface has a default static IP address. Note that for multi-lane protocols, such as 100 GbE, a single interface is used (sfpX).
The configuration files for these network interfaces are stored in: <code>/data/network/</code>

{| class="wikitable"
|-
! Interface Name
! Description
! Default Configuration
! Configuration File
! Example: X4_200/X4_400 FPGA image
|-
| eth0
| RJ45
| style="vertical-align:middle; background-color:#FFF;" | DHCP
| style="vertical-align:middle; background-color:#FFF;" | eth0.network
| DHCP
|-
| int0
| Internal
| style="vertical-align:middle; background-color:#FFF;" | 169.254.0.1/24
| style="vertical-align:middle; background-color:#FFF;" | int0.network
| style="vertical-align:middle; background-color:#FFF;" | 169.254.0.1/24
|-
| sfp0
| QSFP28 0 (4-lanes interface or lane 0)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.10.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.10.2/24
|-
| style="background-color:#FFF;" | sfp0_1
| QSFP28 0 (lane 1)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.11.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0_1.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.11.2/24
|-
| style="background-color:#FFF;" | sfp0_2
| QSFP28 0 (lane 2)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.12.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0_2.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.12.2/24
|-
| sfp0_3
| QSFP28 0 (lane 3)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.13.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0_3.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.13.2/24
|-
| sfp1
| QSFP28 1 (4-lanes interface or lane 0)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.20.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
| sfp1_1
| QSFP28 1 (lane 1)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.21.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1_1.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
| style="background-color:#FFF;" | sfp1_2
| QSFP28 1 (lane 2)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.22.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1_2.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
| style="background-color:#FFF;" | sfp1_3
| QSFP28 1 (lane 3)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.23.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1_3.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
|}

==Network Connectivity==
Once the X4x0 has booted, determine the IP address and verify network connectivity by running uhd_find_devices on the host computer:

X410:
<pre>
$ uhd_find_devices

-- UHD Device 0

Device Address:
serial: 1234ABC
addr: 10.2.161.10
claimed: False
mgmt_addr: 10.2.161.10
product: x410
type: x4xx
</pre>

X440:
<pre>
$ uhd_find_devices

-- UHD Device 0

Device Address:
serial: 1234ABC
addr: 10.2.161.10
claimed: False
mgmt_addr: 10.2.161.10
product: x440
type: x4xx
</pre>

By default, an X4x0 will use DHCP to attempt to find an address.

At this point, you should run:

<code>uhd_usrp_probe --args addr=<IP address></code>
to ensure functionality of the device.

Note: If you receive the following error:

<code>Error: RuntimeError: Graph edge list is empty for rx channel 0</code>
then you will need to download a UHD-compatible FPGA as described in Updating the FPGA or using the following command (it assumes that FPGA images have been downloaded previously using uhd_images_downloader, or that the command is run on the device itself):

X410:
<code>uhd_image_loader --args type=x4xx,addr=<ip address>,fpga=X4_200</code>

X440:
<code>uhd_image_loader --args type=x4xx,addr=<ip address>,fpga=X4_400</code>

When running on the device, use <code>127.0.0.1</code> as the IP address.

You can now use existing UHD examples or applications (such as rx_sample_to_file, rx_ascii_art_dft, or tx_waveforms) or other UHD-compatible applications to start receiving and transmitting with the device.

See Network Interfaces for further details on the various network interfaces available on the X4x0.

===Network Status LEDs===
The Ettus USRP X4x0 is equipped with status LEDs for its network-capable ports: RJ45 and QSFP28s, see RJ45 LED Behavior and QSFP28 LED Behavior accordingly.

====RJ45 LED Behavior====
The RJ45 port has two independent LEDs: green (right) and yellow (left). The table below summarizes the LEDs' behavior. Note that link speed indication is not currently supported.

{| class="wikitable"
|- style="font-weight:bold; text-align:center; vertical-align:middle;"
! Link / Activity
! Green LED
! Yellow LED
|-
| style="vertical-align:middle; background-color:#FFF;" | No Link
| Off
| Off
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / No Activity
| On
| Off
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / Activity
| On
| Blinking
|}

====QSFP28 LED Behavior====
Each QSFP28 connector has four LEDs, one for each high-speed transceiver lane. The table below summarizes the LEDs' behavior, note that for multi-lane protocols, such as 100 GbE, the corresponding LEDs are ganged together. Within the same image, multiple speeds on the same port (e.g., both 10 GbE and 100 GbE) are not supported, therefore link speed indication is not supported.

{| class="wikitable"
|- style="font-weight:bold; text-align:center; vertical-align:middle;"
! Link / Activity
! QSFP28 LED (4 Total)
|-
| style="vertical-align:middle; background-color:#FFF;" | No Link
| Off
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / No Activity
| Green (solid)
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / Activity
| Amber (blinking)
|}

==Security-related Settings==
The X4x0 ships without a root password set. It is possible to ssh into the device by simply connecting as root, and thus gaining access to all subsystems. To set a password, run the command

<code>$ passwd</code>
on the device.

==Serial Connection==
It is possible to gain access to the device using a serial terminal emulator. To do so, the USB debug port needs to be connected to a separate computer to gain access. Most Linux, OSX, or other Unix flavors have a tool called 'screen' which can be used for this purpose, by running the following command:

<code>$ sudo screen /dev/ttyUSB2 115200</code>
In this command, we prepend 'sudo' to elevate user privileges (by default, accessing serial ports is not available to regular users), we specify the device node (in this case, /dev/ttyUSB2), and the baud rate (115200).

The exact device node depends on your operating system's driver and other USB devices that might be already connected. Modern Linux systems offer alternatives to simply trying device nodes; instead, the OS might have a directory of symlinks under /dev/serial/by-id:

<pre>$ ls /dev/serial/by-id
usb-Digilent_Digilent_USB_Device_2516351DDCC0-if02-port0
usb-Digilent_Digilent_USB_Device_2516351DDCC0-if03-port0
</pre>

Note: Exact names depend on the host operating system version and may differ.

The first (with the if02 suffix) connects to the STM32 microcontroller (SCU), whereas the second (with the if03 suffix) connects to Linux running on the RFSoC APU.

<code>$ sudo screen /dev/serial/by-id/usb-Digilent_Digilent_USB_Device_2516351DDCC0-if03-port0 115200</code>
After entering the username root (no password is set by default), you should be presented with a shell prompt similar to the following:

<code>root@ni-x4xx-1234ABC:~#</code>
On this prompt, you can enter any Linux command available. Using the default configuration, the serial console will also show all kernel log messages (unlike when using SSH, for example), and give access to the boot loader (U-boot prompt). This can be used to debug kernel or bootloader issues more efficiently than when logged in via SSH.

==Connecting to the Microcontroller==
The microcontroller (which controls the power sequencing, among other things) also has a serial console available. To connect to the microcontroller, use the other UART device. In the example above:

<code>$ sudo screen /dev/serial/by-id/usb-Digilent_Digilent_USB_Device_2516351DDCC0-if02-port0 115200</code>

It provides a very simple prompt. The command 'help' will list all available commands. A direct connection to the microcontroller can be used to hard-reset the device without physically accessing it and other low-level diagnostics. For example, running the command reboot will emulate a reset button press, resetting the state of the device, while the command powerbtn will emulate a power button press, turning the device back on again.

==SSH Connection==
The USRP X4x0 has two network connections: The dual QSFP28 ports, and an RJ45 connector. The latter is by default configured by DHCP; by plugging it into into 1 Gigabit switch on a DHCP-capable network, it will get assigned an IP address and thus be accessible via ssh.

In case your network setup does not include a DHCP server, refer to the section Serial Connection. A serial login can be used to assign an IP address manually.

After the device obtained an IP address you can log in from a Linux or OSX machine by typing:

<code>$ ssh root@ni-x4xx-1234ABC # Replace with your actual device name!</code>
Depending on your network setup, using a .local domain may work:

<code>$ ssh root@ni-x4xx-1234ABC.local</code>
Of course, you can also connect to the IP address directly if you know it (or set it manually using the serial console).

Note: The device's hostname is derived from its serial number by default (<code>ni-x4xx-$SERIAL</code>). You can change the hostname by creating the file <code>/data/network/hostname</code>, saving the desired hostname in it, then rebooting.

On Microsoft Windows, the connection can be established using a tool such as PuTTY, by selecting a username of root without password.

Like with the serial console, you should be presented with a prompt like the following:

<code>root@ni-x4xx-1234ABC:~#</code>

== Autoboot ==

The USRP X4x0 can be configured to power on and boot automatically when power is applied. This setting can be controlled using the <code>eeprom-set-autoboot</code> script. This script is executed directly on the USRP X4x0. To enable autoboot, run <code>eeprom-set-autoboot on</code>; to disable autoboot, run <code>eeprom-set-autoboot off</code>.

==Updating the FPGA==

The FPGA can be updated simply using uhd_image_loader:

<code>uhd_image_loader --args type=x4xx,addr=<IP address of device> --fpga-path <path to .bit></code>
or

<code>uhd_image_loader --args type=x4xx,addr=<IP address of device>,fpga=FPGA_TYPE</code>
A UHD install will likely have pre-built images in /usr/share/uhd/images/. Up-to-date images can be downloaded using the uhd_images_downloader script:

<code>uhd_images_downloader</code>
will download images into /usr/share/uhd/images/ (the path may differ, depending on how UHD was installed).

Also note that the USRP already ships with compatible FPGA images on the device - these images can be loaded by SSH'ing into the device and running:

X410:
<code>uhd_image_loader --args type=x4xx,mgmt_addr=127.0.0.1,fpga=X4_200</code>

X440:
<code>uhd_image_loader --args type=x4xx,mgmt_addr=127.0.0.1,fpga=X4_400</code>

==FPGA Image Flavors==
Unlike the USRP X310 or other third-generation USRP devices, the FPGA image flavors do not only encode how the QSFP28 connectors are configured, but also which master clock rates are available. This is because the data converter configuration is part of the FPGA image (the ADCs/DACs on the X4x0 are on the same die as the FPGA). The image flavors consist of two short strings, separated by an underscore, e.g. X4_200 (X410) or X4_400 (X440) is an image flavor which contains 4x 10 GbE, and can handle an analog bandwidth of 200 MHz or 400 MHz respectively. The first two characters describe the configuration of the QSFP28 ports: 'X' stands for 10 GbE, 'C' stands for 100 GbE. For details see [https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_updating_fpga_types FPGA Image Flavor] in the [https://files.ettus.com/manual USRP Hardware Driver and USRP Manual].

The analog bandwidth determines the available master clock rates.

X410: As of UHD 4.1, only the X4_200 image is shipped with UHD, which allows a 245.76 MHz or 250 MHz master clock rate. With UHD 4.2, the CG_400 image was added allowing for 491.52 MHz and 500 MHz master clock rates. With UHD 4.5, the UC_200 image (245.76 MHz and 250 MHz master clock rate) was added.

X440: As of UHD 4.5, UHD ships with X4_400, X4_1600, CG_400 and CG_1600 images. The X4_400 and CG_400 images allow master clock rates between 125 MHz and 512 MHz and the usage of all 8 channels while the X4_1600 and CG_1600 images allow master clock rates between 125 MHz and 2048 MHz but only the usage of channels 0 and 4.

Any other images are considered experimental (unsupported).

==Device Arguments==

{| class="wikitable" style="vertical-align:middle;"
|- style="font-weight:bold; text-align:center;"
! Key
! Description
! Example Value
|-
| addr
| IPv4 address of primary SFP+ port to connect to.
| addr=192.168.30.2
|-
| second_addr
| IPv4 address of secondary SFP+ port to connect to.
| second_addr=192.168.40.2
|-
| mgmt_addr
| IPv4 address or hostname to which to connect the RPC client. Defaults to `addr'.
| mgmt_addr=ni-sulfur-311FE00
|-
| find_all
| When using broadcast, find all devices, even if unreachable via CHDR.
| find_all=1
|-
| master_clock_rate
| Master Clock Rate in Hz.
| master_clock_rate=250e6
|-
| converter_rate
| Converter Rate in Hz. Only X440 and together with master_clock_rate.
| master_clock_rate=250e6,converter_rate=1000e6
|-
| serialize_init
| Force serial initialization of daughterboards.
| serialize_init=1
|-
| skip_init
| Skip the initialization process for the device.
| skip_init=1
|-
| time_source
| Specify the time (PPS) source.
| time_source=internal
|-
| clock_source
| Specify the reference clock source.
| clock_source=internal
|-
| ref_clk_freq
| Specify the external reference clock frequency, default is 10 MHz.
| ref_clk_freq=20e6
|-
| discovery_port
| Override default value for MPM discovery port.
| discovery_port=49700
|-
| rpc_port
| Override default value for MPM RPC port.
| rpc_port=49701
|}

This is only a subset of the existing device arguments. For a complete list please consult the [https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_usage_args UHD user manual of the X4x0 device series].

==GPS==

The USRP X4x0 includes a Jackson Labs LTE-Lite GPS module. Its antenna port is on the rear panel. When the X4x0 has access to GPS satellite signals, it can use this module to read out the current GPS time and location as well as to discipline an onboard OCXO.

To use the GPS as a clock and time reference, set the device arguments <code>time_source</code> and <code>clock_source</code> to <code>gpsdo</code>.

Note the GPS module is not enabled when the clock source is not set to <code>gpsdo</code>.

Its power-on status can be queried using the <code>gps_enabled</code> GPS sensor. When disabled, none of the sensors will return useful
(if any) values.

Note that acquiring a GPS lock can take some time after enabling the GPS, so if a UHD application is enabling the GPS dynamically, it might take some time before a GPS lock is reported.

To set the clock source and time source dynamically, see the following code:

<pre>
// Set clock/time individually:
usrp->set_clock_source("gpsdo");
usrp->set_time_source("gpsdo");
// This is equivalent to the previous commands, but faster, as it sets
// both settings simultaneously and avoids duplicating settings that are shared
// between these calls.
usrp->set_sync_source("clock_source=gpsdo,time_source=gpsdo");
</pre>

==Front-Panel Programmable GPIOs==

The USRP X4x0 has two HDMI front-panel connectors, which are connected to the FPGA. For a
description of the GPIO control API, see the
[https://files.ettus.com/manual/page_x400_gpio_api.html USRP X4x0 GPIO UHD Manual Entry],
[https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_usage_gpio the USRP X4x0 Series Manual],
the [https://files.ettus.com/manual/page_zbx.html#zbx_atr ZBX ATR section] (X410) and the
[https://files.ettus.com/manual/page_fbx.html#fbx_atr FBX ATR section] (X440).

==Subdev Specifications==

The RF ports on the front panel of the X410 + ZBX correspond to the following subdev specifications:

{| class="wikitable"
|-
! Label
! style="text-align:center; vertical-align:middle; font-weight:bold;" | Subdev Spec
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 0
| A:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 1
| A:1
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 0
| B:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 1
| B:1
|}

The RF ports on the front panel of the X440 + FBX correspond to the following subdev specifications (for xx_400 FPGA images):

{| class="wikitable"
|-
! Label
! style="text-align:center; vertical-align:middle; font-weight:bold;" | Subdev Spec
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 0
| A:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 1
| A:1
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 2
| A:2
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 3
| A:3
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 0
| B:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 1
| B:1
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 2
| B:2
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 3
| B:3
|}

When using a xx_1600 FPGA image on X440, only A:0 and B:0 are available.

The subdev spec slot identifiers "A" and "B" are not reflected on the front panel. They were set to match valid subdev specifications of previous USRPs, maintaining backward compatibility.

These values can be used for uhd::usrp::multi_usrp::set_rx_subdev_spec() and uhd::usrp::multi_usrp::set_tx_subdev_spec() as with other USRPs.

==Rear Panel Status LEDs==

The USRP X4x0 is equipped with four LEDs located on the device's rear panel. Each LED supports four different states: Off, Green, Red, and Amber. One LED (PWR) indicates the device's power state (see Power LED below). The other three LEDs (LED 0, LED 1, and LED 2) are user-configurable, different behaviors are supported for each of these LEDs (see User-configurable LEDs below).

[[File:x4xx_rearpanel_status_leds.png|125px]]

===X4x0 Rear Panel Status LEDs===
Power LED
The USRP X4x0's PWR LED is reserved to visually indicate the user the device's power state. Power LED Behavior describes what each LED state represents.

===Power LED Behavior===

{| class="wikitable" style="background-color:#FFF;"
|- style="font-weight:bold; text-align:center;"
! PWR LED State
! style="vertical-align:middle;" | Meaning
|- style="vertical-align:middle;"
| Off
| No power is applied
|- style="vertical-align:middle;"
| Amber
| Power is good but X4x0 is powered off
|- style="vertical-align:middle;"
| Green
| Power is good and X4x0 is powered on
|- style="vertical-align:middle;"
| Red
| Power error state
|}

===User-configurable LEDs===
The USRP X4x0's user-configurable rear panel status LEDs (LED 0, LED 1, and LED 2) allow the user to have visual indication of various device conditions. Supported LED Behaviors provides a complete list of the supported behaviors for each user-configurable LED. By default, these LEDs are configured as described in LEDs Default Behavior.

The user may alter the default LEDs behavior either temporarily or persistently, see the Temporarily change the LED Behavior or Persistently in the UHD manual to change the LED Behavior accordingly.

https://files.ettus.com/manual/page_usrp_x4xx.html

==Technical Support and Community Knowledge Base==
Technical support for USRP hardware is available through email only. If the product arrived in a nonfunctional state or you require technical assistance, please contact [mailto:support@ettus.com support@ettus.com]. Please allow 24 to 48 hours for response by email, depending on holidays and weekends, although we are often able to reply more quickly than that.

We also recommend that you subscribe to the community mailing lists. The mailing lists have a responsive and knowledgeable community of hundreds of developers and technical users who are located around the world. When you join the community, you will be connected to this group of people who can help you learn about SDR and respond to your technical and specific questions. Often your question can be answered quickly on the mailing lists. Each mailing list also provides an archive of all past conversations and discussions going back many years. Your question or problem may have already been addressed before, and a relevant or helpful solution may already exist in the archive.

Discussions involving the USRP hardware and the UHD software itself are best addressed through the '''usrp-users''' mailing list at [http://usrp-users.ettus.com http://usrp-users.ettus.com].

Discussions involving the use of [http://gnuradio.org/ GNU Radio] with USRP hardware and UHD software are best addressed through the '''discuss-gnuradio''' mailing list at [https://lists.gnu.org/mailman/listinfo/discussgnuradio https://lists.gnu.org/mailman/listinfo/discussgnuradio].

Discussions involving the use of [http://openbts.org/ OpenBTS®] with USRP hardware and UHD software are best addressed through the '''openbts-discuss''' mailing list at [https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss].

The support page on our website is located at [https://www.ettus.com/support https://www.ettus.com/support]. The Knowledge Base is located at [https://kb.ettus.com https://kb.ettus.com].

==Legal Considerations==
Every country has laws governing the transmission and reception of radio signals. Users are solely responsible for insuring they use their USRP system in compliance with all applicable laws and regulations. Before attempting to transmit and/or receive on any frequency, we recommend that you determine what licenses may be required and what restrictions may apply.

*NOTE: This USRP product is a piece of test equipment.

==Sales and Ordering Support==
If you have any non-technical questions related to your order, then please contact us by email at [mailto:orders@ettus.com orders@ettus.com], or by phone at +14086106399 (Monday-Friday, 8 AM - 5 PM, Pacific Time). Please be sure to include your order number and the serial number of your USRP.

==Terms and Conditions of Sale==
Terms and conditions of sale can be accessed online at the following link: http://www.ettus.com/legal/terms-and-conditions-of-sale

[[Category:Getting Started Guides]]
[[Category:X4x0]]

USRP X410/X440 Getting Started Guide

2024-11-05T20:47:27Z

DylanCaswell:

==Kit Contents==
===X4x0===
{|
|style="vertical-align:top"|
* NI Ettus USRP X410 or X440
* DC Power Supply (12V, 20A)
* 1 Gigabit Ethernet Cat-5e Cable (3m)
* USB-A to USB-C Cable (1m)
* Getting Started Guide URL (QR Code)
* Safety, Environmental, and Regulatory Information
||[[File:X410.jpg|450px|center]]
||[[File:X440.jpg|450px|center]]
|}

==USRP X440 Design Considerations==
* https://kb.ettus.com/About_Sampling_Rates_and_Master_Clock_Rates_for_the_USRP_X440

==You Will Need==
* For Network Mode: A host computer with an available 1 or 10 Gigabit Ethernet interface for sample streaming. In addition to the Ethernet interface used for sampling streaming, your host computer will require a separate 1 Gigabit Ethernet interface for command and control streaming.

* For Stand-Alone Embedded Mode: A host computer with an available 1 Gigabit Ethernet port or a USB 2.0 port to remotely access the embedded Linux operating system running on ARM CPU.

==Proper Care and Handling==

All Ettus Research products are individually tested before shipment. The USRP is guaranteed to be functional at the time it is received by the customer. Improper use or handling of the USRP can cause the device to become non-functional. Take the following precautions to prevent damage to the unit.

* Never allow metal objects to touch the circuit board while powered.
* Always properly terminate the transmit port with an antenna or 50Ω load.
* Always handle the board with proper anti-static methods.
* Never allow the board to directly or indirectly come into contact with any voltage spikes.
* Never allow any water or condensing moisture to come into contact with the device.
* Always use caution with FPGA, firmware, or software modifications.

{|
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |X410: Never apply more than +14 dBm continuous <=3GHz, +17 dBm continuous >3GHz, or +20dBm more than 5 minutes >3GHz of power into any RF input.
|-
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |X440: Never apply more than +13 dBm continuous <=2.5GHz, +17 dBm continuous between 2.5GHz and 3.6 GHz, or +20dBm continuous between 3.6 GHz and 4 GHz of power into any RF input.
|-
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |[[File:Caution.png|24px|center]]
|style="padding-left:10px; padding-right:10px; padding-bottom:10px;" |X410: Always use at least 30dB attenuation if operating in loopback configuration.
|-
|}

==Install and Setup the Software Tools on Your Host Computer==
In order to use your Universal Software Radio Peripheral (USRP™), you must have the software tools correctly installed and configured on your host computer. The easiest way to install USRP Hardware Driver (UHD) is by getting a binary installer package for your operating system as described in the UHD manual about [https://files.ettus.com/manual/page_install.html Binary Installation]. If no binary packages are available for your operating system or you want to modify the sources by yourself, a step-by-step guide is available at the Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on [[Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on Linux|Linux]], [[Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on OS X|OS X]] and [[Building and Installing the USRP Open Source Toolchain (UHD and GNU Radio) on Windows|Windows]] Application Notes.

To find the latest release of UHD, see the UHD repository at https://github.com/EttusResearch/uhd.

The USRP X410 requires UHD version 4.1 or later.
The USRP X440 requires UHD version 4.5 or later.

'''When you receive a brand-new device, it is strongly recommended that you download the latest filesystem image from the Ettus Research website update the unit. It is not recommended that you use the filesystem from the factory as-is. Instructions on downloading the latest filesystem image and updating it is listed below.'''

'''Note that if you are operating the device in Network Mode, the version of UHD running on the host computer and the USRP X4x0 must match.'''

==Assembling the X4x0==
Inside the kit you will find the X4x0 and an X4x0 power supply. Plug these in, connect the 1GbE RJ45 interface to your network, and power on the device by pressing the power button.

==The STM32 Microcontroller==

The STM32 microcontroller (also referred to as the "SCU") controls various low-level features of the X4x0 series motherboard: It controls the power sequencing, reads out fan speeds and some of the temperature sensors. It is connected to the RFSoC via an I2C bus. It is running software based on Chromium EC.

It is possible to log into the STM32 using the serial interface (see Connecting to the Microcontroller). This will allow certain low-level controls, such as remote power cycling should the CPU have become unresponsive for whatever reason.

===Updating the SCU===

The writable SCU image file is stored on the filesystem under /lib/firmware/ni/ec-titanium-revX.RW.bin (where X is a revision compatibility number). To update, simply replace the .bin file with the updated version and reboot.

==eMMC Storage==

The main non-volatile storage of the USRP is a 16 GB eMMC storage. This storage can be made accessible as a USB Mass Storage device through the USB-OTG connector on the back panel.

The entire root file system (Linux kernel, libraries) and any user data are stored on the eMMC. It is partitioned into four partitions:

Boot partition (contains the bootloader). This partition usually does not require modification.
A data partition, mounted in /data. This is the only partition that is not erased during file system updates.
Two identical system partitions (root file systems). These contain the operating system and the home directory (anything mounted under / that is not the data or boot partition). The reason there are two of these is to enable remote updates: An update running on one partition can update the other one without any effect to the currently running system. Note that the system partitions are erased during updates and are thus unsuitable for permanently storing information.
Note: It is possible to access the currently inactive root file system by mounting it. After logging into the device using serial console or SSH (see the following two sections), run the following commands:

<pre>
$ mkdir temp

$ mount /dev/mmcblk0p3 temp # This assumes mmcblk0p3 is currently not mounted

$ ls temp # You are now accessing the idle partition:

bin data etc lib media proc sbin tmp usr
boot dev home lost+found mnt run sys uboot var
</pre>

The device node in the mount command might differ, depending on which partition is currently already mounted.

==USB Access to eMMC==

While Mender should be used for routine filesystem updates (see Updating Filesystems), it is also possible to access the X4x0's internal eMMC from an external host over USB. This allows accessing or modifying the filesystem, as well as the ability to flash the device with an entirely new filesystem.

In order to do so, you'll need an external computer with two USB ports, and two USB cables to connect the computer to your X4x0. The instructions below assume a Linux host.

First, connect to the APU serial console at a baud rate of 115200. Boot the device, and stop the boot sequence by typing noautoboot at the prompt. Then, run the following command in the U-boot command prompt:

<code>ums 0 mmc 0</code>

This will start the USB mass storage gadget to expose the eMMC as a USB mass storage device. You should see a spinning indicator on the console, which indicates the gadget is active.

Next, connect your external computer to the X4x0's USB to PS port using an OTG cable. Your computer should recognize the X4x0 as a mass storage device, and you should see an entry in your kernel logs (dmesg) that looks like this:

<pre>
usb 3-1: New USB device found, idVendor=3923, idProduct=7a7d, bcdDevice= 2.23
usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 3-1: Product: USB download gadget
usb 3-1: Manufacturer: National Instruments
sd 6:0:0:0: [sdc] 30932992 512-byte logical blocks: (15.8 GB/14.8 GiB)
sdc: sdc1 sdc2 sdc3 sdc4
sd 6:0:0:0: [sdc] Attached SCSI removable disk
</pre>

The exact output will depend on your machine, but from this log you can see that the X4x0 was recognized and /dev/sdc is the block device representing the eMMC, with 4 partitions detected (see eMMC Storage for details on the partition layout).

It is now possible to treat the X4x0's eMMC as you would any other USB drive: the individual partitions can be mounted and accessed, or the entire block device can be read/written.

Once you're finished accessing the device over USB, the u-boot gadget may be stopped by hitting Ctrl-C at the APU serial console.

== Flashing the eMMC ==

Once the X4x0's eMMC is accessible over USB, it's possible to write the filesystem image and thus change the device's filesystem. You can obtain the latest filesystem image by running:

<code>uhd_images_downloader -t sdimg -t x4xx</code>

The output of this command will indicate where the downloaded images were put, or specify a custom location using using the <code>-i INSTALL_LOCATION</code> argument.

There are 2 ways to write the image to the X4x0's eMMC: using <code>dd</code> and <code>bmaptool</code>. Run one of the following commands, replacing <code>/dev/sdX</code> with the block device of the X4x0's eMMC (found in the device's kernel log or by running <code>lsblk</code>). Take care to use the correct block device or else you might overwrite the wrong drive!

<code>sudo dd if=/path/to/usrp_x4xx_fs.sdimg of=/dev/sdX bs=1M</code>

<code>sudo bmaptool copy --bmap /path/to/usrp_x4xx_fs.sdimg.bmap /path/to/usrp_x4xx_fs.sdimg /dev/sdX</code>

The former is generally preferred as it will always work, even if it slower than the latter.

==Using a USRP X4x0 from UHD==
Like any other USRP, all X4x0 USRPs are controlled by the UHD software. To integrate a USRP X4x0 into your C++ application, you would generate a UHD device in the same way you would for any other USRP:

<code>auto usrp = uhd::usrp::multi_usrp::make("type=x4xx");</code>

For a list of which arguments can be passed into make(), see Section Device Arguments.

==Updating Filesystems==

Mender is a third-party software that enables remote updating of the root file system without physically accessing the device (see also the [https://mender.io/ Mender website]). Mender can be executed locally on the device, or a Mender server can be set up which can be used to remotely update an arbitrary number of USRP devices. Mender servers can be self-hosted, or hosted by Mender (see mender.io for pricing and availability).

When updating the file system using Mender, the tool will overwrite the root file system partition that is not currently mounted (note: the onboard flash storage contains two separate root file system partitions, only one is ever used at a single time). Any data stored on that partition will be permanently lost, including the currently loaded FPGA image. After updating that partition, it will reboot into the newly updated partition. Only if the update is confirmed by the user, the update will be made permanent. This means that if an update fails, the device will be always able to reboot into the partition from which the update was originally launched (which presumably is in a working state). Another update can be launched now to correct the previous, failed update, until it works.

To obtain the file system Mender image (these are files with a <code>.mender</code> suffix), run the following command on the host computer with Internet access:

$ sudo uhd_images_downloader -t mender -t x4xx --yes

NOTE: In the output of the command, the folder destination where the images are saved is printed out.

Next, you will need to copy this Mender file system image to the USRP X4xx. This can be done with the Linux utility <code>scp</code>.

$ scp /usr/local/share/uhd/images/usrp_x4xx_fs.mender root@192.168.1.51:~/.

Note: The path and IP may different for your configuration, the command above assumes you're using the default installation path of <code>/usr/local</code> and that the X4xx's IP is <code>192.168.1.51</code>.

After copying the Mender file system image to the X4xx, connect to the X4xx using either the Serial Console, or via SSH to gain shell access.

On the X4xx, run <code>mender install /path/to/latest.mender</code> to update the file system:

$ mender install /home/root/usrp_x4xx_fs.mender

The artifact can also be stored on a remote server:
$ mender install <nowiki>http://server.name/path/to/latest.mender</nowiki>

This procedure will take a few minutes to complete. After mender has logged a successful update, reboot the device:
$ reboot

If the reboot worked, and the device seems functional, commit the changes so that the boot loader knows to permanently boot into this partition:
$ mender -commit

To identify the currently installed Mender artifact from the command line, the following file can be queried on the X4x0:
$ cat /etc/mender/artifact_info

If you are using a Mender server, the updates can be initiated from a web dashboard. From there, you can start the updates without having to log into the device, and you can update groups of USRPs with a few clicks in a web GUI. The dashboard can also be used to inspect the state of USRPs. This is a simple way to update groups of rack-mounted USRPs with custom file systems.

If you are running a hosted server, the updates can be initiated from a web dashboard. From there, you can start the updates without having to log into the device, and can update groups of USRPs with a few clicks in a web GUI. The dashboard can also be used to inspect the state of USRPs. This is a simple way to update groups of rack-mounted USRPs with custom file systems.

==Network Interfaces==
The Ettus USRP X4x0 has various network interfaces:

eth0: RJ45 port.

The RJ45 port comes up with a default configuration of DHCP, that will request a network address from your DHCP server (if available on your network). This interface is agnostic of FPGA image flavor.

int0: internal interface for network communication between the embedded ARM processor and FPGA.

The internal network interface is configured with a static address: 169.254.0.1/24. This interface is agnostic of FPGA image flavor.

sfpX [, sfpX_1, sfpX_2, sfpX_3]: QSFP28 network interface(s), up-to four (one per lane) based on implemented protocol.

Each QSFP28 port has four high-speed transceiver lanes. Therefore, depending on the FPGA image flavor, up-to four different network interfaces may exist per QSFP28 port, using the sfpXfor the first lane, and sfpX_1-3 for the other three lanes. Each network interface has a default static IP address. Note that for multi-lane protocols, such as 100 GbE, a single interface is used (sfpX).
The configuration files for these network interfaces are stored in: <code>/data/network/</code>

{| class="wikitable"
|-
! Interface Name
! Description
! Default Configuration
! Configuration File
! Example: X4_200/X4_400 FPGA image
|-
| eth0
| RJ45
| style="vertical-align:middle; background-color:#FFF;" | DHCP
| style="vertical-align:middle; background-color:#FFF;" | eth0.network
| DHCP
|-
| int0
| Internal
| style="vertical-align:middle; background-color:#FFF;" | 169.254.0.1/24
| style="vertical-align:middle; background-color:#FFF;" | int0.network
| style="vertical-align:middle; background-color:#FFF;" | 169.254.0.1/24
|-
| sfp0
| QSFP28 0 (4-lanes interface or lane 0)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.10.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.10.2/24
|-
| style="background-color:#FFF;" | sfp0_1
| QSFP28 0 (lane 1)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.11.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0_1.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.11.2/24
|-
| style="background-color:#FFF;" | sfp0_2
| QSFP28 0 (lane 2)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.12.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0_2.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.12.2/24
|-
| sfp0_3
| QSFP28 0 (lane 3)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.13.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp0_3.network
| style="vertical-align:middle; background-color:#FFF;" | 192.168.13.2/24
|-
| sfp1
| QSFP28 1 (4-lanes interface or lane 0)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.20.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
| sfp1_1
| QSFP28 1 (lane 1)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.21.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1_1.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
| style="background-color:#FFF;" | sfp1_2
| QSFP28 1 (lane 2)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.22.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1_2.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
| style="background-color:#FFF;" | sfp1_3
| QSFP28 1 (lane 3)
| style="vertical-align:middle; background-color:#FFF;" | 192.168.23.2/24
| style="vertical-align:middle; background-color:#FFF;" | sfp1_3.network
| style="vertical-align:middle; background-color:#FFF;" | N/C
|-
|}

==Network Connectivity==
Once the X4x0 has booted, determine the IP address and verify network connectivity by running uhd_find_devices on the host computer:

X410:
<pre>
$ uhd_find_devices

-- UHD Device 0

Device Address:
serial: 1234ABC
addr: 10.2.161.10
claimed: False
mgmt_addr: 10.2.161.10
product: x410
type: x4xx
</pre>

X440:
<pre>
$ uhd_find_devices

-- UHD Device 0

Device Address:
serial: 1234ABC
addr: 10.2.161.10
claimed: False
mgmt_addr: 10.2.161.10
product: x440
type: x4xx
</pre>

By default, an X4x0 will use DHCP to attempt to find an address.

At this point, you should run:

<code>uhd_usrp_probe --args addr=<IP address></code>
to ensure functionality of the device.

Note: If you receive the following error:

<code>Error: RuntimeError: Graph edge list is empty for rx channel 0</code>
then you will need to download a UHD-compatible FPGA as described in Updating the FPGA or using the following command (it assumes that FPGA images have been downloaded previously using uhd_images_downloader, or that the command is run on the device itself):

X410:
<code>uhd_image_loader --args type=x4xx,addr=<ip address>,fpga=X4_200</code>

X440:
<code>uhd_image_loader --args type=x4xx,addr=<ip address>,fpga=X4_400</code>

When running on the device, use <code>127.0.0.1</code> as the IP address.

You can now use existing UHD examples or applications (such as rx_sample_to_file, rx_ascii_art_dft, or tx_waveforms) or other UHD-compatible applications to start receiving and transmitting with the device.

See Network Interfaces for further details on the various network interfaces available on the X4x0.

===Network Status LEDs===
The Ettus USRP X4x0 is equipped with status LEDs for its network-capable ports: RJ45 and QSFP28s, see RJ45 LED Behavior and QSFP28 LED Behavior accordingly.

====RJ45 LED Behavior====
The RJ45 port has two independent LEDs: green (right) and yellow (left). The table below summarizes the LEDs' behavior. Note that link speed indication is not currently supported.

{| class="wikitable"
|- style="font-weight:bold; text-align:center; vertical-align:middle;"
! Link / Activity
! Green LED
! Yellow LED
|-
| style="vertical-align:middle; background-color:#FFF;" | No Link
| Off
| Off
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / No Activity
| On
| Off
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / Activity
| On
| Blinking
|}

====QSFP28 LED Behavior====
Each QSFP28 connector has four LEDs, one for each high-speed transceiver lane. The table below summarizes the LEDs' behavior, note that for multi-lane protocols, such as 100 GbE, the corresponding LEDs are ganged together. Within the same image, multiple speeds on the same port (e.g., both 10 GbE and 100 GbE) are not supported, therefore link speed indication is not supported.

{| class="wikitable"
|- style="font-weight:bold; text-align:center; vertical-align:middle;"
! Link / Activity
! QSFP28 LED (4 Total)
|-
| style="vertical-align:middle; background-color:#FFF;" | No Link
| Off
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / No Activity
| Green (solid)
|-
| style="vertical-align:middle; background-color:#FFF;" | Link / Activity
| Amber (blinking)
|}

==Security-related Settings==
The X4x0 ships without a root password set. It is possible to ssh into the device by simply connecting as root, and thus gaining access to all subsystems. To set a password, run the command

<code>$ passwd</code>
on the device.

==Serial Connection==
It is possible to gain access to the device using a serial terminal emulator. To do so, the USB debug port needs to be connected to a separate computer to gain access. Most Linux, OSX, or other Unix flavors have a tool called 'screen' which can be used for this purpose, by running the following command:

<code>$ sudo screen /dev/ttyUSB2 115200</code>
In this command, we prepend 'sudo' to elevate user privileges (by default, accessing serial ports is not available to regular users), we specify the device node (in this case, /dev/ttyUSB2), and the baud rate (115200).

The exact device node depends on your operating system's driver and other USB devices that might be already connected. Modern Linux systems offer alternatives to simply trying device nodes; instead, the OS might have a directory of symlinks under /dev/serial/by-id:

<pre>$ ls /dev/serial/by-id
usb-Digilent_Digilent_USB_Device_2516351DDCC0-if02-port0
usb-Digilent_Digilent_USB_Device_2516351DDCC0-if03-port0
</pre>

Note: Exact names depend on the host operating system version and may differ.

The first (with the if02 suffix) connects to the STM32 microcontroller (SCU), whereas the second (with the if03 suffix) connects to Linux running on the RFSoC APU.

<code>$ sudo screen /dev/serial/by-id/usb-Digilent_Digilent_USB_Device_2516351DDCC0-if03-port0 115200</code>
After entering the username root (no password is set by default), you should be presented with a shell prompt similar to the following:

<code>root@ni-x4xx-1234ABC:~#</code>
On this prompt, you can enter any Linux command available. Using the default configuration, the serial console will also show all kernel log messages (unlike when using SSH, for example), and give access to the boot loader (U-boot prompt). This can be used to debug kernel or bootloader issues more efficiently than when logged in via SSH.

==Connecting to the Microcontroller==
The microcontroller (which controls the power sequencing, among other things) also has a serial console available. To connect to the microcontroller, use the other UART device. In the example above:

<code>$ sudo screen /dev/serial/by-id/usb-Digilent_Digilent_USB_Device_2516351DDCC0-if02-port0 115200</code>

It provides a very simple prompt. The command 'help' will list all available commands. A direct connection to the microcontroller can be used to hard-reset the device without physically accessing it and other low-level diagnostics. For example, running the command reboot will emulate a reset button press, resetting the state of the device, while the command powerbtn will emulate a power button press, turning the device back on again.

==SSH Connection==
The USRP X4x0 has two network connections: The dual QSFP28 ports, and an RJ45 connector. The latter is by default configured by DHCP; by plugging it into into 1 Gigabit switch on a DHCP-capable network, it will get assigned an IP address and thus be accessible via ssh.

In case your network setup does not include a DHCP server, refer to the section Serial Connection. A serial login can be used to assign an IP address manually.

After the device obtained an IP address you can log in from a Linux or OSX machine by typing:

<code>$ ssh root@ni-x4xx-1234ABC # Replace with your actual device name!</code>
Depending on your network setup, using a .local domain may work:

<code>$ ssh root@ni-x4xx-1234ABC.local</code>
Of course, you can also connect to the IP address directly if you know it (or set it manually using the serial console).

Note: The device's hostname is derived from its serial number by default (<code>ni-x4xx-$SERIAL</code>). You can change the hostname by creating the file <code>/data/network/hostname</code>, saving the desired hostname in it, then rebooting.

On Microsoft Windows, the connection can be established using a tool such as PuTTY, by selecting a username of root without password.

Like with the serial console, you should be presented with a prompt like the following:

<code>root@ni-x4xx-1234ABC:~#</code>

== Autoboot ==

The USRP X4x0 can be configured to power on and boot automatically when power is applied. This setting can be controlled using the <code>eeprom-set-autoboot</code> script. This script is executed directly on the USRP X4x0. To enable autoboot, run <code>eeprom-set-autoboot on</code>; to disable autoboot, run <code>eeprom-set-autoboot off</code>.

==Updating the FPGA==

The FPGA can be updated simply using uhd_image_loader:

<code>uhd_image_loader --args type=x4xx,addr=<IP address of device> --fpga-path <path to .bit></code>
or

<code>uhd_image_loader --args type=x4xx,addr=<IP address of device>,fpga=FPGA_TYPE</code>
A UHD install will likely have pre-built images in /usr/share/uhd/images/. Up-to-date images can be downloaded using the uhd_images_downloader script:

<code>uhd_images_downloader</code>
will download images into /usr/share/uhd/images/ (the path may differ, depending on how UHD was installed).

Also note that the USRP already ships with compatible FPGA images on the device - these images can be loaded by SSH'ing into the device and running:

X410:
<code>uhd_image_loader --args type=x4xx,mgmt_addr=127.0.0.1,fpga=X4_200</code>

X440:
<code>uhd_image_loader --args type=x4xx,mgmt_addr=127.0.0.1,fpga=X4_400</code>

==FPGA Image Flavors==
Unlike the USRP X310 or other third-generation USRP devices, the FPGA image flavors do not only encode how the QSFP28 connectors are configured, but also which master clock rates are available. This is because the data converter configuration is part of the FPGA image (the ADCs/DACs on the X4x0 are on the same die as the FPGA). The image flavors consist of two short strings, separated by an underscore, e.g. X4_200 (X410) or X4_400 (X440) is an image flavor which contains 4x 10 GbE, and can handle an analog bandwidth of 200 MHz or 400 MHz respectively. The first two characters describe the configuration of the QSFP28 ports: 'X' stands for 10 GbE, 'C' stands for 100 GbE. For details see [https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_updating_fpga_types FPGA Image Flavor] in the [https://files.ettus.com/manual USRP Hardware Driver and USRP Manual].

The analog bandwidth determines the available master clock rates.

X410: As of UHD 4.1, only the X4_200 image is shipped with UHD, which allows a 245.76 MHz or 250 MHz master clock rate. With UHD 4.2, the CG_400 image was added allowing for 491.52 MHz and 500 MHz master clock rates. With UHD 4.5, the UC_200 image (245.76 MHz and 250 MHz master clock rate) was added.

X440: As of UHD 4.5, UHD ships with X4_400, X4_1600, CG_400 and CG_1600 images. The X4_400 and CG_400 images allow master clock rates between 125 MHz and 512 MHz and the usage of all 8 channels while the X4_1600 and CG_1600 images allow master clock rates between 125 MHz and 2048 MHz but only the usage of channels 0 and 4.

Any other images are considered experimental (unsupported).

==Device Arguments==

{| class="wikitable" style="vertical-align:middle;"
|- style="font-weight:bold; text-align:center;"
! Key
! Description
! Example Value
|-
| addr
| IPv4 address of primary SFP+ port to connect to.
| addr=192.168.30.2
|-
| second_addr
| IPv4 address of secondary SFP+ port to connect to.
| second_addr=192.168.40.2
|-
| mgmt_addr
| IPv4 address or hostname to which to connect the RPC client. Defaults to `addr'.
| mgmt_addr=ni-sulfur-311FE00
|-
| find_all
| When using broadcast, find all devices, even if unreachable via CHDR.
| find_all=1
|-
| master_clock_rate
| Master Clock Rate in Hz.
| master_clock_rate=250e6
|-
| converter_rate
| Converter Rate in Hz. Only X440 and together with master_clock_rate.
| master_clock_rate=250e6,converter_rate=1000e6
|-
| serialize_init
| Force serial initialization of daughterboards.
| serialize_init=1
|-
| skip_init
| Skip the initialization process for the device.
| skip_init=1
|-
| time_source
| Specify the time (PPS) source.
| time_source=internal
|-
| clock_source
| Specify the reference clock source.
| clock_source=internal
|-
| ref_clk_freq
| Specify the external reference clock frequency, default is 10 MHz.
| ref_clk_freq=20e6
|-
| discovery_port
| Override default value for MPM discovery port.
| discovery_port=49700
|-
| rpc_port
| Override default value for MPM RPC port.
| rpc_port=49701
|}

This is only a subset of the existing device arguments. For a complete list please consult the [https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_usage_args UHD user manual of the X4x0 device series].

==GPS==

The USRP X4x0 includes a Jackson Labs LTE-Lite GPS module. Its antenna port is on the rear panel. When the X4x0 has access to GPS satellite signals, it can use this module to read out the current GPS time and location as well as to discipline an onboard OCXO.

To use the GPS as a clock and time reference, set the device arguments <code>time_source</code> and <code>clock_source</code> to <code>gpsdo</code>.

Note the GPS module is not enabled when the clock source is not set to <code>gpsdo</code>.

Its power-on status can be queried using the <code>gps_enabled</code> GPS sensor. When disabled, none of the sensors will return useful
(if any) values.

Note that acquiring a GPS lock can take some time after enabling the GPS, so if a UHD application is enabling the GPS dynamically, it might take some time before a GPS lock is reported.

To set the clock source and time source dynamically, see the following code:

<pre>
// Set clock/time individually:
usrp->set_clock_source("gpsdo");
usrp->set_time_source("gpsdo");
// This is equivalent to the previous commands, but faster, as it sets
// both settings simultaneously and avoids duplicating settings that are shared
// between these calls.
usrp->set_sync_source("clock_source=gpsdo,time_source=gpsdo");
</pre>

Note the GPS module is not always enabled. Its power-on status can be queried using the gps_enabled GPS sensor (see also The Sensor API). When disabled, none of the sensors will return useful (if any) values.

When selecting gpsdo as a clock source, the GPS will always be enabled. Note that acquiring a GPS lock can take some time after enabling the GPS, so if a UHD application is enabling the GPS dynamically, it might take some time before a GPS lock is reported.

==Front-Panel Programmable GPIOs==

The USRP X4x0 has two HDMI front-panel connectors, which are connected to the FPGA. For a
description of the GPIO control API, see the
[https://files.ettus.com/manual/page_x400_gpio_api.html USRP X4x0 GPIO UHD Manual Entry],
[https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_usage_gpio the USRP X4x0 Series Manual],
the [https://files.ettus.com/manual/page_zbx.html#zbx_atr ZBX ATR section] (X410) and the
[https://files.ettus.com/manual/page_fbx.html#fbx_atr FBX ATR section] (X440).

==Subdev Specifications==

The RF ports on the front panel of the X410 + ZBX correspond to the following subdev specifications:

{| class="wikitable"
|-
! Label
! style="text-align:center; vertical-align:middle; font-weight:bold;" | Subdev Spec
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 0
| A:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 1
| A:1
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 0
| B:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 1
| B:1
|}

The RF ports on the front panel of the X440 + FBX correspond to the following subdev specifications (for xx_400 FPGA images):

{| class="wikitable"
|-
! Label
! style="text-align:center; vertical-align:middle; font-weight:bold;" | Subdev Spec
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 0
| A:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 1
| A:1
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 2
| A:2
|- style="vertical-align:middle; background-color:#FFF;"
| DB 0 / RF 3
| A:3
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 0
| B:0
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 1
| B:1
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 2
| B:2
|- style="vertical-align:middle; background-color:#FFF;"
| DB 1 / RF 3
| B:3
|}

When using a xx_1600 FPGA image on X440, only A:0 and B:0 are available.

The subdev spec slot identifiers "A" and "B" are not reflected on the front panel. They were set to match valid subdev specifications of previous USRPs, maintaining backward compatibility.

These values can be used for uhd::usrp::multi_usrp::set_rx_subdev_spec() and uhd::usrp::multi_usrp::set_tx_subdev_spec() as with other USRPs.

==Rear Panel Status LEDs==

The USRP X4x0 is equipped with four LEDs located on the device's rear panel. Each LED supports four different states: Off, Green, Red, and Amber. One LED (PWR) indicates the device's power state (see Power LED below). The other three LEDs (LED 0, LED 1, and LED 2) are user-configurable, different behaviors are supported for each of these LEDs (see User-configurable LEDs below).

[[File:x4xx_rearpanel_status_leds.png|125px]]

===X4x0 Rear Panel Status LEDs===
Power LED
The USRP X4x0's PWR LED is reserved to visually indicate the user the device's power state. Power LED Behavior describes what each LED state represents.

===Power LED Behavior===

{| class="wikitable" style="background-color:#FFF;"
|- style="font-weight:bold; text-align:center;"
! PWR LED State
! style="vertical-align:middle;" | Meaning
|- style="vertical-align:middle;"
| Off
| No power is applied
|- style="vertical-align:middle;"
| Amber
| Power is good but X4x0 is powered off
|- style="vertical-align:middle;"
| Green
| Power is good and X4x0 is powered on
|- style="vertical-align:middle;"
| Red
| Power error state
|}

===User-configurable LEDs===
The USRP X4x0's user-configurable rear panel status LEDs (LED 0, LED 1, and LED 2) allow the user to have visual indication of various device conditions. Supported LED Behaviors provides a complete list of the supported behaviors for each user-configurable LED. By default, these LEDs are configured as described in LEDs Default Behavior.

The user may alter the default LEDs behavior either temporarily or persistently, see the Temporarily change the LED Behavior or Persistently in the UHD manual to change the LED Behavior accordingly.

https://files.ettus.com/manual/page_usrp_x4xx.html

==Technical Support and Community Knowledge Base==
Technical support for USRP hardware is available through email only. If the product arrived in a nonfunctional state or you require technical assistance, please contact [mailto:support@ettus.com support@ettus.com]. Please allow 24 to 48 hours for response by email, depending on holidays and weekends, although we are often able to reply more quickly than that.

We also recommend that you subscribe to the community mailing lists. The mailing lists have a responsive and knowledgeable community of hundreds of developers and technical users who are located around the world. When you join the community, you will be connected to this group of people who can help you learn about SDR and respond to your technical and specific questions. Often your question can be answered quickly on the mailing lists. Each mailing list also provides an archive of all past conversations and discussions going back many years. Your question or problem may have already been addressed before, and a relevant or helpful solution may already exist in the archive.

Discussions involving the USRP hardware and the UHD software itself are best addressed through the '''usrp-users''' mailing list at [http://usrp-users.ettus.com http://usrp-users.ettus.com].

Discussions involving the use of [http://gnuradio.org/ GNU Radio] with USRP hardware and UHD software are best addressed through the '''discuss-gnuradio''' mailing list at [https://lists.gnu.org/mailman/listinfo/discussgnuradio https://lists.gnu.org/mailman/listinfo/discussgnuradio].

Discussions involving the use of [http://openbts.org/ OpenBTS®] with USRP hardware and UHD software are best addressed through the '''openbts-discuss''' mailing list at [https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss https://lists.sourceforge.net/lists/listinfo/openbtsdiscuss].

The support page on our website is located at [https://www.ettus.com/support https://www.ettus.com/support]. The Knowledge Base is located at [https://kb.ettus.com https://kb.ettus.com].

==Legal Considerations==
Every country has laws governing the transmission and reception of radio signals. Users are solely responsible for insuring they use their USRP system in compliance with all applicable laws and regulations. Before attempting to transmit and/or receive on any frequency, we recommend that you determine what licenses may be required and what restrictions may apply.

*NOTE: This USRP product is a piece of test equipment.

==Sales and Ordering Support==
If you have any non-technical questions related to your order, then please contact us by email at [mailto:orders@ettus.com orders@ettus.com], or by phone at +14086106399 (Monday-Friday, 8 AM - 5 PM, Pacific Time). Please be sure to include your order number and the serial number of your USRP.

==Terms and Conditions of Sale==
Terms and conditions of sale can be accessed online at the following link: http://www.ettus.com/legal/terms-and-conditions-of-sale

[[Category:Getting Started Guides]]
[[Category:X4x0]]

X440

2024-01-31T22:47:05Z

DylanCaswell:

== Notice ==
'''When you receive a brand-new device, it is strongly recommended that you download the most recent filesystem image from the Ettus Research website and write it to the NI Ettus USRP X4x0. Instructions on downloading the latest filesystem image and writing it to the X4x0 are described in the [https://kb.ettus.com/USRP_X410/X440_Getting_Started_Guide USRP X4x0 Getting Started Guide].'''

'''Note that if you are operating the device in Network Mode, then the versions of UHD running on the host computer and on the NI Ettus USRP X4x0 device must match.'''

== Device Overview ==
===X440===
The NI Ettus USRP X440 is the widest bandwidth USRP software defined radio device. It differs architecturally from most USRPs, utilizing a direct sampling architecture that provides balun-coupled access to the ADCs and DACs on the onboard Xilinx Zynq RFSoC. This makes it well suited to use as an intermediate frequency transceiver, connecting to external front ends for applications like satellite communications (SATCOM) prototyping, SATCOM ground station deployment, and mmWave or sub-THz 6G research. USRP X440 features high channel density – 8 Tx and 8 Rx channels per device – with phase coherency across channels by sharing sample clocks. Therefore, it is ideal for applications like direction finding and radar research and prototyping.

== Key Features==

===X440===
{|
|style="vertical-align:top"|
* High channel density
* Reliable and fault-tolerant deployment
* Stand-alone (embedded) or host-based (network streaming) operation
* Fully integrated and assembled (the USRP X440 does not support swappable daughtercards)
* 30 MHz to 4 GHz frequency range (tunable down to 1MHz)
* Up to 1600 MHz of instantaneous bandwidth per channel
* 8 RX, 8 TX in half-wide RU form factor
* Xilinx Zynq-Ultrascale+ ZU28DR RFSoC
* 12 bit ADC, 14 bit DAC
* IQ Sample Clock rates up to 2000 MS/s
* Onboard SD-FEC, DDC, DUC
* Quad-core ARM Cortex-A53 up to 1.2 GHz CPU
* Dual-core ARM Cortex-A5 MPCore up to 500 MHz
* Two QSFP28 ports (10 Gigabit Ethernet, 100 Gigabit Ethernet)
* RJ45 (1 GbE) [1]
* 10 MHz Clock reference
* PPS time reference
* Trig In/Out Interface
* Built-in GPSDO
* Two FPGA Programmable GPIO Interfaces (HDMI)
* 1 Type C USB host port
* 1 Type C USB port (serial console, JTAG)
* Watchdog timer
* OpenEmbedded Linux
* USRP Hardware Driver™ (UHD) open-source software API version 4.5.0 or later
* RF Network on Chip (RFNoC™) FPGA development framework
* Xilinx Vivado® 2021.1 Design Suite (license not included)
* GNU Radio support maintained by Ettus Research™ through GR-UHD, an interface to UHD distributed by GNU Radio
* [1] The RJ45 port is used for remote management of the device and does not support IQ streaming.

|[[File:X440.jpg|500px|center]]

|}

==Hardware Specifications==
===X440===
* Current Hardware Revision: Module revision D and Motherboard revision F
* Minimum version of UHD required: 4.5.0
* USRP X440 is covered by Export Administration Regulations (EAR) NS2. Refer to [https://www.bis.doc.gov/ US Department of Commerce] for details and country chart.

https://www.ni.com/docs/en-US/bundle/ettus-usrp-x440-specs/page/specs.html
https://github.com/EttusResearch/uhd/releases/tag/v4.5.0.0

===CAD/STP Models===

If you want any CAD / STP models beyond those found here, please send an email to Ettus Support at [mailto:support@ettus.com support@ettus.com] noting your request and your use case for any such model. We will determine on a case-by-case basis whether we have any such requested model and, if so, whether to release it -- possibly requiring an NDA for any such release. Note that we do not have models on all USRPs and daughterboards, and requesting any model does not guarantee that either Ettus Research or NI will honor any such request.

==FPGA==
===FPGA User Modifications===
The Verilog code for the FPGA in the NI Ettus USRP X4x0 is open-source, and users are free to modify and customize it for their needs. However, certain modifications may result in either bricking the device, or even in physical damage to the unit. Specifically, changing the I/O interface of the FPGA in any way, or modifying the pin and timing constraint files, could result in physical damage to other components on the motherboard, external to the FPGA, and doing this will void the warranty. Also, even if the PCIe interface is not being used, you cannot remove or reassign these pins in the constraint file. The constraint files should not be modified. Please note that modifications to the FPGA are made at the risk of the user, and may not be covered by the warranty of the device.

==Interfaces and Connectivity==

===Front Panel===

====X440====

[[File:x440_front_panel.jpg|500px|center]]

===Rear Panel===

[[File:x440_back_panel.jpg|500px|center]]

===Ref Clock - 10 MHz===
Using an external 10 MHz reference clock, a square wave will offer the best phase noise performance, but a sinusoid is acceptable.

===PPS - Pulse Per Second===
Using a PPS signal for timestamp synchronization requires a square wave signal (a typical PPS signal has a 20%-25% duty cycle) with a 5 Vpp amplitude.

To test the PPS input, you can use the following tool from the UHD examples:

* <code><args></code> are device address arguments (optional if only one USRP device is on your machine)

cd <install-path>/lib/uhd/examples ./test_pps_input –args=<args>

===Front Panel GPIO===
* https://files.ettus.com/manual/page_x400_gpio_api.html#x4x0gpio_fpanel

====Power on state====

* https://kb.ettus.com/USRP_X410/X440_Getting_Started_Guide#Autoboot
* https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_usage_rearpanelleds_power

==Accessories==

For datasheet, drawings, pricing, and purchasing please search for the Part Number listed below via https://www.ni.com/en-us/search.html

* Dual 100 Gigabit Ethernet PCIe Interface Kit For Ettus USRP X4xx
** Part Number: 788216-01

* USRP X4xx Power Supply, 100-240VAC 50/60HZ 12VDC 24AMP
** Part Number: 788204-01

* QSFP28 To 4xSFP28 Breakout Cable, 1M
** Part Number: 788214-01

* QSFP28 Twinaxial Cable, 3M
** Part Number: 788215-03

* USRP X4xx 19" Rack Mount Accessory, 1U, 2 USRP X4xx Devices, Shoulder to Shoulder
** Part Number: 788147-01

* USRP X4xx Desktop Stack Accessory, Single USRP X4xx Device Fastened Buildup
** Part Number: 788148-01

* USRP X4xx 19" Rack Mount Accessory, 1U, 1 USRP X4xx Device, w/Surrogate Extension
** Part Number: 788149-01

* GPIO Communication Cable
** SHH19-H19-AUX Shielded Single-Ended Cable, 1M
*** Part Number: 152629-01
** SHH19-H19-AUX Shielded Single-Ended Cable, 2M
*** Part Number: 152629-02

* SCB-19 Noise Rejecting, Shielded Aux I/O Connector
** Part Number: 782444-01

* Fan Replacement Cartridges
** USRP X4xx Fan Cartridge Accessory, Exhaust
*** Part Number: 788164-01
** USRP X4xx Fan Cartridge Accessory, Intake
*** Part Number: 788165-01

==10 Gigabit Ethernet==
'''Recommended 10 Gigabit Ethernet Cards'''
* Dual 10 Gigabit Ethernet Interface for Ettus USRP
** [https://search.ni.com/nisearch/app/main/p/bot/no/ap/global/lang/en/pg/1/q/788600-01/ ni.com part number 788600-01]
* Intel X710-DA2
** [http://ark.intel.com/products/83964/Intel-Ethernet-Converged-Network-Adapter-X710-DA2 Intel® Ethernet Converged Network Adapter X710-DA2 ]
* Intel X710-DA4
** [http://ark.intel.com/products/83965/Intel-Ethernet-Converged-Network-Adapter-X710-DA4 Intel® Ethernet Converged Network Adapter X710-DA4 ]

==100 Gigabit Ethernet==

===X440===

* Requires UHD 4.5 or later: https://github.com/EttusResearch/uhd/releases/tag/v4.5.0.0
* 100GbE Streaming only supports Linux Hosts

'''Recommended 100 Gigabit Ethernet Cards'''
* Mellanox/NVIDIA ConnectX-5 EX 100 GbE NIC (MCX516A-CDAT (PCIe Gen4 x16))

'''Recommended 100 Gigabit Ethernet Cables'''
* Mellanox/NVIDIA 3m QSFP28 MCP1600-C003E26N
** Shorter length variants also recommended

'''Recommended Host PC'''
* At least 32 CPU Cores
* At least 64 GB RAM
* Ubuntu 20.04 (5.13.0-44-generic)

''' Validated Hardware and Software Configuration Examples '''
* Ubuntu 20.04 (5.13.0-44-generic kernel), DPDK 20.11, with AMD Ryzen Threadripper 3960X 24-Core Processor - 48 CPU - 3.6 GHz CPU freq - 64 GB RAM. Mellanox/NVIDIA ConnectX-5 EX 100 GbE NIC (MCX516A-CDAT (PCIe Gen4 x16)). Mellanox/NVIDIA 3m QSFP28 MCP1600-C003E26N cables.

''' Data Throughput Rates '''

Testing was completed with the following conditions
* Hardware and Software Configurations listed above
* CPU configured for performance mode: https://kb.ettus.com/USRP_Host_Performance_Tuning_Tips_and_Tricks#CPU_Governor
* DPDK Setup: https://files.ettus.com/manual/page_dpdk.html and https://kb.ettus.com/Getting_Started_with_DPDK_and_UHD#UHD_4.0
* Enabling Tx pause Frames on X4x0 for the SFP port(s) utilized for streaming: https://files.ettus.com/manual/page_transport.html#transport_udp_linux
** <code>ethtool -A sfp0 tx on</code>
** <code>ethtool -A sfp1 tx on</code>
* uhd.conf: See https://files.ettus.com/manual/page_dpdk.html#dpdk_nic_config

Executing [https://github.com/EttusResearch/uhd/blob/UHD-4.5/host/examples/benchmark_rate.cpp benchmark_rate ] over multiple iterations as well as over an extended continuous time period (>12 Hours) without data loss resulted in the following maximum rates and channel counts
* Usage of the <code>--priority</code> argument set to <code>high</code> in benchmark_rate which requires benchmark rate to be executed with root privileges via <code>sudo</code>
* Usage of single versus multiple threads in the benchmark_rate utility - controlled by using the <code>--multi_streamer</code> argument. Specifying this argument assigns one thread per channel being streamed.
* Utilizing the CG_400 and CG_1600 bitfile.

* CG_400
** Dual Port DPDK
*** 6 Rx @ 500 MS/s
*** 8 Rx @ 400 MS/s
*** 6 Tx @ 500 MS/s
*** 8 Tx @ 450 MS/s
*** 4 Rx + 4 Tx @ 500 MS/s
*** 8 Rx + 8 Tx @ 250 MS/s
* CG_1600
** Dual Port DPDK
*** 2 Rx @ 1000 MS/s
*** 2 Tx @ 1800 MS/s
*** 2 Rx + 2 Tx @ 1000 MS/s

All testing was done using dual 100GbE ports. For a single port, expect around half the number of channels as compared to the dual port equivalent configuration at the same streaming rate.

==Guidance on SFP+ Adapters for Fiber Connectivity on NI Ettus USRP X4x0==

Ettus Research currently offers direct-connect, copper cabling accessories for the NI Ettus USRP X4x0. However, it is also possible to use multi-mode fiber instead of copper connections for these devices. In this section, we will provide general guidance on the types of fiber adapters and cables that can be used with these products.

The NI Ettus USRP X4x0 is compatible with most brands of SFP+ fiber adapters. In some cases, other equipment in the systems such as 1/10/100 Gigabit Ethernet switches are only compatible with specific brands of SFP+ adapters and cables. As a general rule, we recommend checking compatibility with the switches and network cards in your system before purchasing an adapter.

Ettus Research does test the NI Ettus USRP X4x0 devices with the listed hardware as noted in the above section https://kb.ettus.com/X440#100_Gigabit_Ethernet

==Certifications==
===RoHS===
As of December 1st, 2010 all Ettus Research products are RoHS compliant unless otherwise noted. More information can be found at [http://ettus.com/legal/rohs-information http://ettus.com/legal/rohs-information]

===China RoHS===
'''Management Methods for Controlling Pollution Caused by Electronic Information Products Regulation'''

'''Chinese Customers'''

National Instruments is in compliance with the Chinese policy on the Restriction of Hazardous Substances (RoHS) used in Electronic Information Products. For more information about the National Instruments China RoHS compliance, visit [http://www.ni.com/environment/rohs_china ni.com/environment/rohs_china].

==Certificate / Letter of Volatility==

Certifications will soon be findable on the [https://www.ni.com/en/support/documentation/product-certifications.html NI Product Certifications lookup tool].

[https://www.ni.com/docs/en-US/bundle/ni-ettus-usrp-x440-lov/resource/ni-ettus-usrp-x440-lov.pdf The Letter of Volatility Link.]

==Downloads==
[http://files.ettus.com/manual/md_fpga.html FPGA Resources]

[http://files.ettus.com/binaries/uhd_stable/ UHD Stable Binaries]

[https://github.com/EttusResearch/uhd UHD Source Code on Github]

[[Category:Hardware Resources]]

File:ANxxx-500-1500 1250e6 2560e6.jpg

2023-11-17T19:09:32Z

DylanCaswell: DylanCaswell uploaded a new version of File:ANxxx-500-1500 1250e6 2560e6.jpg

File:ANxxx-500-1500 512e6 4096e6.jpg

2023-11-17T19:09:20Z

DylanCaswell: DylanCaswell uploaded a new version of File:ANxxx-500-1500 512e6 4096e6.jpg

File:ANxxx-500-1500 450e6 3600e6.jpg

2023-11-17T19:09:10Z

DylanCaswell: DylanCaswell uploaded a new version of File:ANxxx-500-1500 450e6 3600e6.jpg

File:ANxxx-500-1500 400e6 3200e6.jpg

2023-11-17T19:08:59Z

DylanCaswell: DylanCaswell uploaded a new version of File:ANxxx-500-1500 400e6 3200e6.jpg

File:AN055-L-band-dual-rate.jpg

2023-11-17T19:08:15Z

DylanCaswell: DylanCaswell uploaded a new version of File:AN055-L-band-dual-rate.jpg

Graph that shows how the L-band spectrum can be captured by using two different master clock rates (and with this two ADC/DAC converter rates) on a USRP X440.

About Sampling Rates and Master Clock Rates for the USRP X440

2023-11-17T19:05:31Z

DylanCaswell:

== Application Note Number and Authors ==

'''AN-055''' by Marian Koop


<span id="overview"></span>
= Overview =
This application note guides users through the selection process of Master Clock Rates (MCR) for the [https://kb.ettus.com/X440#X440 USRP X440]. It will highlight possible implications and side effects as well as design specific differences to other USRPs (like the X410).

<span id="x440-cfg_considerations"></span>
= USRP X440 Configuration Considerations =
The USRP X440 is a [https://uhd.readthedocs.io/en/latest/page_fbx.html#fbx_too balun-coupled transceiver] without built-in RF signal conditioning. Compared to other RF architectures this enables the USRP X440 to access the full RF bandwidth available to the ADC/DAC, but also requires additional frequency planning. To achieve this, the USRP X440 utilizes its ADC/DAC in direct sampling mode and is susceptible to various effects that may distort the signal of interest. These can be separated into distortions from both signal processing and from the ADC/DAC design.

<span id="converter_rate-mcr-iq_rate"></span>
== Relationship between RF-ADC/DAC Converter Rate, USRP Master Clock Rate (MCR), Data IQ rate ==
Except for the 200 MHz variant, the default USRP X440 FPGA images do not contain a configurable DDC<ref>Digital Down Conversion</ref>/DUC<ref>Digital Up Conversion</ref> block. This means that the IQ sample rate (F<sub>IQ</sub>) is the same as the Master Clock Rate (MCR) that goes into the RFNoC Radio block. However, unlike most other USRPs the USRP X440 supports a highly variable MCR. The RF Data Converter sampling rate (F<sub>S</sub>) is chosen by UHD based on the MCR and the available resampling factors of 2, 4, or 8, and defaults to the highest achievable values with these factors. This can be overridden if the desired MCR can be achieved with multiple converter rates (see device argument [https://uhd.readthedocs.io/en/latest/page_usrp_x4xx.html#x4xx_usage_args converter_rate]). The inverse calculation - divide the converter rate by 8, 4 or 2 - has to be done to derive the master clock rate if a specific converter rate shall be used. Figure 1 depicts the simplified signal path block diagram for the USRP X440.

{| class="wikitable" style="text-align: center; border-style: none; background-color:#ffffff;"
|+ Figure 1. Simplified USRP X440 Signal Path
|-
| style="border-style: none;" | [[File:ANxxx-X440_signal_path.jpg|450px|center]]
|}

<span id="dsp-distortions"></span>
== Aliases and Nyquist Zones ==
By itself the USRP X440 can sample input signals at frequencies above the Nyquist frequency<ref>[https://en.wikipedia.org/wiki/Nyquist_frequency Nyquist frequency]</ref>, which is half of the ADC converter sampling rate (F<sub>S</sub>). However, this method introduces aliasing effects, which cause unwanted signals to appear as mirror images around multiples of the Nyquist frequency (F<sub>S</sub>/2) in the output spectrum. The first Nyquist zone (N1) is the frequency range from 0 to F<sub>S</sub>/2, and the second Nyquist zone (N2) goes from F<sub>S</sub>/2 to F<sub>S</sub>. Other Nyquist zones are numbered in ascending order, each spanning F<sub>S</sub>/2. The digital passband in each Nyquist zone can be calculated as 0.4 * F<sub>S</sub> (see also <ref>[https://docs.xilinx.com/r/en-US/pg269-rf-data-converter/RF-ADC-Decimation-Filters-Gen-1/Gen-2 Xilinx RF-ADC Decimation Filters (Gen-1)]</ref>). The following figure depicts the Nyquist zones for the minimum and maximum RF-ADC converter rates supported by the USRP X440. Note that the illustrations do not show the effects of external, analog filters on the achievable passband within a Nyquist zone. A typical expectation is, that the unusable frequency range around each Nyquist zone boundary (also often referred to as a guard band) increases with ascending Nyquist zone order and results in decreasing, lopsided achievable passbands.
{| class="wikitable" style="text-align: center; border-style: none; background-color:#ffffff;"
|+ Figure 2. Nyquist Zones
|-
| style="border-style: none;" | [[File:ANxxx-X440_nyquist_zones.jpg|450px|center]]
|}

Knowledge of signal aliases can both be exploited and create uncertainties. Applications could utilize intentional under sampling (also referred as "bandpass sampling") to receive signals at greater than F<sub>S</sub>/2. The same effect may on the other hand lead to garbled or distorted signal detection if the signal of interest spans multiple Nyquist zones or interferer signals are aliased into the observed spectrum. Both effects are depicted in figure 3.

{| class="wikitable" style="text-align: center; border-style: none; background-color:#ffffff;"
|+ Figure 3. Aliases - Wanted and unwanted
|-
| style="border-style: none;" | [[File:ANxxx-wanted_and_unwanted_aliases.jpg|450px|center]]
|}

Applications should therefore prefer converter rates that can contain the desired signal spectrum in a single Nyquist zone, or split the signal spectrum among multiple channels and devices. While the USRP X440 does not limit the utilized Nyquist zone, performance degrades in higher orders zones and application should focus on operating in Nyquist zones 1 and 2 (For RX, zone 3 is possible, but zones 4 and higher result into significant performance degradation).

<span id="adc-distortions"></span>
== RF-ADC Spurs to consider and how to predict them ==
Another kind of distortion originates from the ADC/DAC itself. The USRP X440 uses the Xilinx RFDC, which is a design that combines multiple converters to
achieve high RF-ADC rates. An RF-ADC in this design has 8 sub-ADCs that are interleaved together. The resulting offset spurs are minimized by the integrated self-calibration (see also <ref>[https://docs.xilinx.com/r/en-US/pg269-rf-data-converter/Key-CAL-Features-and-Guidance-Summary Key CAL Features and Guidance Summary]</ref>) executed by UHD but may still be detectable in the signal spectrum.

{| class="wikitable" style="text-align: center; border-style: none; background-color:#ffffff;"
|+ Figure 4. RF-ADC Spurs with MCR = 500 MHz
|-
| style="border-style: none;" | [[File:ANxxx-adc_distortions.jpg|450px|center]]
|}

Even with the best calibration the RF-ADC spurs may still be detectable in the captured spectrum. Knowledge of the location of the spurs, in particular the RF-ADC offset spur may be used during frequency planning to select an MCR (and converter rate) that exclude the offset spur frequencies from the capture spectrum. RF-ADC input spurs on the other hand will be more difficult to avoid, but as rule of thumb for modulated input signals carrier frequencies that fall on an RF-ADC offset spur frequency should be avoided (because offset and input spurs would superimpose each other).

=== How to predict offset spurs ===
Any residual DC offset not corrected appears as a spur at k*F<sub>S</sub>/N, where F<sub>S</sub> is the composite converter rate of the RF-ADC, N is the number of sub-RF-ADCs interleaved together (8 for X4xx devices), and k = 0, 1, 2, … N.
For more information on expected spurs levels, refer to OIS at <ref>[https://docs.xilinx.com/r/en-US/ds926-zynq-ultrascale-plus-rfsoc/RF-ADC-Performance-Characteristics RF-ADC Performance Characteristics]</ref>.

=== How to predict input spurs ===
Any residual difference from gain and time skew correction results in spurious signals at +/-f<sub>in</sub> + (k/N)*F<sub>S</sub>, where F<sub>S</sub> is the converter rate of the RF-ADC, N is the number of sub-RF-ADCs (8 for X4xx devices), and f<sub>in</sub> is the frequency of the input signal.
For more information on expected spurs levels, refer to GTIS at <ref>[https://docs.xilinx.com/r/en-US/ds926-zynq-ultrascale-plus-rfsoc/RF-ADC-Performance-Characteristics RF-ADC Performance Characteristics]</ref>.

<span id="dac-distortions"></span>
== RF-DAC Distortions ==
Like the RF-ADC, the RF-DAC is also not an ideal circuitry and suffers from zero-order hold reconstruction. To counter this undesired attenuation in all but the first Nyquist zone, the Xilinx RF-DAC offers a Mix-Mode, which improves the power response in the second Nyquist zone and is utilized by the USRP X440. This, together with an inverse sinc filter to counter residual distortion limits the practical use of the RF-DAC to the first two Nyquist zones. For more information on the RF-DAC mix-mode and inverse sinc filter characteristics, refer to <ref>[https://docs.xilinx.com/r/en-US/pg269-rf-data-converter/RF-DAC-Nyquist-Zone-Operation RF-DAC Nyquist Zone Operation]</ref>.

{| class="wikitable" style="text-align: center; border-style: none; background-color:#ffffff;"
|+ Figure 5 <ref>[https://docs.xilinx.com/viewer/attachment/wIPPkVrh~0jtjy6aqWeihQ/q5kXcl5Z7lFon2v535oW0w Xilinx: Ideal DAC Output Response, Normalised to Fsample]</ref>. RF-DAC Mix-Mode and normal, ideal roll-off sinc response.
|-
| style="border-style: none;" | [[File:ANxxx-dac_roll-off_sinc_response.png|350px|center]]
|}



<span id="dual-rate"></span>
== Dual Rate ==
Unlike previous USRPs, the USRP X440 supports the operation at two different master clock rates simultaneously. All channels on the first daughterboard will run on the first master clock rate / sampling rate and all channels on the second daughterboard will run on the second configured master clock rate / sampling rate. The main motivation for having two different master clock rates is the direct sampling architecture of the USRP X440 without signal conditioning and filtering. While [[#dsp-distortions|Aliases and Nyquist Zones]] describes the challenges of that, with dual rate this feature can be used to capture an RF spectrum that exceeds the bandwidth abilities of the single rate operation. Using a second rate, one can close the Nyquist gap of the other and monitor a wider spectrum for further processing.
As the clocks of both radios are derived from a common clocking chip, not all combinations are possible. Refer to [[#X440-supported-dual-rates|X440 Supported Dual Rates]] for possible RF Data Converter sampling rate combinations. The section about the [[#converter_rate-mcr-iq_rate|Relationship between RFADC/DAC Converter Rate, USRP Master Clock Rate (MCR) and Data IQ rate]] explains how to derive valid master clock rates from the RF Data converter sampling rates.

<span id="use-cases"></span>
= Use cases =
== Scan Spectrum within single Nyquist zone ==
=== Spectrum Capture between 1.7 and 1.9 GHz. ===
* Min Bandwidth: 200 MHz
* Minimum IQ Rate: 250 MSps
==== Option 1: MCR = 250 MHz, RF-ADC converter rate = 2 GHz ====
{| class="wikitable" style="text-align: center; border-style: none; background-color:#ffffff;"
|-
| style="border-style: none;" | [[File:ANxxx-1700-1800_250e6_2000e6.jpg|450px|center]]
|}
This is not the best option because our spectrum of interest is very close to a Nyquist zone boundary.

==== Option 2: MCR = 300 MHz, RF-ADC converter rate = 2.4 GHz ====
{| class="wikitable" style="text-align: center; border-style: none; background-color:#ffffff;"
|-
| style="border-style: none;" | [[File:ANxxx-1700-1800_300e6_2400e6.jpg|450px|center]]
|}
This option is better, the spectrum of interest is well within a Nyquist zone. Within the bandwidth of interest falls one of the ADC offset spurs. If the input signal is relatively strong, the impact from this small spur is negligible. If on the other hand the input signal strength is on the low end (for the X440), then maybe a different MCR should be considered.

==== Option 3: MCR = 320 MHz, RF-ADC converter rate = 2.56 GHz ====
{| class="wikitable" style="text-align: center; border-style: none; background-color:#ffffff;"
|-
| style="border-style: none;" | [[File:ANxxx-1700-1800_320e6_2560e6.jpg|450px|center]]
|}
This option avoids a potential impact of an ADC offset spur in the observed spectrum. The only drawback to option 2 is the slightly higher data rate during host post-processing.

=== Spectrum Capture between 500 MHz and 1.5 GHz. ===
The USRP X440 ships with multiple [https://uhd.readthedocs.io/en/latest/page_usrp_x4xx.html#x4xx_updating_fpga_types FPGA image flavors]. These either support 400 MHz or 1600 MHz RF bandwidth per channel. To address this use case, users have the option of using a bit file with 1600 MHz RF bandwidth to capture a contiguous spectrum, or use a 400 MHz bit file and create a stitched spectrum during host side post-processing.
==== Using 1600 MHz image ====
* Min Bandwidth: 1000 MHz
* Minimum IQ Rate: 1250 MSps
===== Option 1: MCR = 1280 MHz, RF-ADC converter rate = 2.56 GHz =====
{| class="wikitable" style="text-align: center; border-style: none; background-color:#ffffff;"
|-
| style="border-style: none;" | [[File:ANxxx-500-1500_1250e6_2560e6.jpg|450px|center]]
|}
Bad option, because desired spectrum spans multiple Nyquist zones.

===== Option 2: MCR = 1600 MHz, RF-ADC converter rate = 3.2 GHz =====
{| class="wikitable" style="text-align: center; border-style: none; background-color:#ffffff;"
|-
| style="border-style: none;" | [[File:ANxxx-500-1500_1600e6_3200e6.jpg|450px|center]]
|}
This is not the best option because our spectrum of interest is very close to a Nyquist zone boundary.

===== Option 3: MCR = 1689.6 MHz, RF-ADC converter rate = 3.3792 GHz =====
{| class="wikitable" style="text-align: center; border-style: none; background-color:#ffffff;"
|-
| style="border-style: none;" | [[File:ANxxx-500-1500_1689e6_3379e6.jpg|450px|center]]
|}
This option would work. If the input signal strength is low, using an even higher MCR would reduce the number of potential ADC offset spurs. This needs to be traded off against a higher data rate during host post-processing.

==== Using 400 MHz image ====
Due to the smaller bandwidth addressing the use case will require the use of multiple channels. The captured spectra than needs to be stitched (combined) together.
* Max Bandwidth: 400 MHz
===== Option 1: MCR 400 MHz, RF-ADC converter rate = 3.2 GHz, 3 channels =====
{| class="wikitable" style="text-align: center; border-style: none; background-color:#ffffff;"
|-
| style="border-style: none;" | [[File:ANxxx-500-1500_400e6_3200e6.jpg|450px|center]]
|}
This is not the best option because our spectrum of interest boundary is very close to a Nyquist zone boundary.

===== Option 2: MCR 450 MHz, RF-ADC converter rate = 3.6 GHz, 3 channels =====
{| class="wikitable" style="text-align: center; border-style: none; background-color:#ffffff;"
|-
| style="border-style: none;" | [[File:ANxxx-500-1500_450e6_3600e6.jpg|450px|center]]
|}
This option would work. Since the spectrum of interest is larger than the per channel bandwidth the captured spectrum may contain potential ADC offset spurs. For the spectrum of interest the 3 channels would nicely use tune frequencies (680, 1000, 1320 MHz) that do not match ADC offset spur frequencies.

===== Option 3: MCR 512 MHz, RF-ADC converter rate = 4.096 GHz, 3 channels =====
{| class="wikitable" style="text-align: center; border-style: none; background-color:#ffffff;"
|-
| style="border-style: none;" | [[File:ANxxx-500-1500_512e6_4096e6.jpg|450px|center]]
|}
This option would work as well. Like in option 2, the spectrum of interest may contain one potential ADC offset spur (compared to 2 in option 2). The drawback to option 2 is of course again the higher data rate during host post-processing that may be offset by only having to stitch less spectra (2 vs 3) together.



== Scan Spectrum with dual master clock rate ==
=== Spectrum capture between 1.0 and 2.4 GHz (L-band) ===
* Combination of two RF-ADC converter rates: 4096 MHz and 2560 MHz
* Derived master clock rates: 1024 MHz (resampling factor 4) and 1280 MHz (resampling factor 2). The resampling factors are chosen to produce master clock rates which allow capturing a sufficient bandwidth to not have any gaps.
* Center frequencies: 1.23 GHz and 2.0 GHz respectively
* 1600 MHz FPGA image required due to the bandwidth requirements
{| class="wikitable" style="text-align: center; border-style: none; background-color:#ffffff;"
|-
| style="border-style: none;" | [[File:AN055-L-band-dual-rate.jpg|800px|center]]
|}
In the picture you can see a light-green band between 1.0 GHz and 2.4 GHz which can be covered using two different rates: Radio0 operates at MCR=1024 MHz in its first Nyquist zone and radio1 operates at 1280 MHz in its second Nyquist zone. The coverage is shown as light-blue boxes in both frequency charts. Starting with UHD 4.6, the X440_L_band_capture.py example demonstrates this use case and by default uses center frequencies of 0.9 GHz and 2 GHz respectively. These were choosen to conveniently display the two individual spectra next to each other in a continuous spectra view without any overlap. Practical applications on the other hand need to take into account that the well usable bandwidth of each channel is only about 0.8 * MCR. For the chosen MCRs this means that the first radio has a usable bandwidth of 819.2 MHz and the second one of 1024 MHz. Taking into account that a typical RF passband in the first Nyquist zone has a passband of up to 0.4 * F<sub>S</sub> and the need for some overlap of the two spectra, the center frequency of radio0 should be set to 1.230 GHz (usable bandwidth spans from ~820 MHz to ~1640 MHz). Radio1 will be used in its second Nyquist zone, so the center frequency should be 2.0 GHz (usable bandwidth from ~1.5 GHz to ~2.5 GHz).

<span id="appendix"></span>
= Appendix =
<span id="x440-mcrs"></span>
== X440 Supported Master Clock Rates (MCR) ==
Note: The selected FPGA bitfile may further limit the maximum supported master clock rate.
{| class="wikitable" style="text-align: center; margin:auto"
|-
! MCR (MHz) !! RFDC Converter Rate (GHz)
|-
| 125.0 || 1.0
|-
| 128.0 || 1.024
|-
| 133.12 || 1.06496
|-
| 150.0 || 1.2
|-
| 153.6 || 1.2288
|-
| 160.0 || 1.28
|-
| 163.84 || 1.31072
|-
| 184.32 || 1.47456
|-
| 199.68 || 1.59744
|-
| 200.0 || 1.6
|-
| 204.8 || 1.6384
|-
| 240.0 || 1.92
|-
| 245.76 || 1.96608
|-
| 250.0 || 2.0, 1.0
|-
| 256.0 || 2.048, 1.024
|-
| 266.24 || 2.12992, 1.06496
|-
| 300.0 || 2.4, 1.2
|-
| 307.2 || 2.4576, 1.2288
|-
| 320.0 || 2.56, 1.28
|-
| 327.68 || 2.62144, 1.31072
|-
| 360.0 || 2.88, 1.44
|-
| 368.64 || 1.47456, 2.94912
|-
| 375.0 || 3.0, 1.5
|-
| 384.0 || 1.536, 3.072
|-
| 399.36 || 3.19488, 1.59744
|-
| 400.0 || 3.2, 1.6
|-
| 409.6 || 3.2768, 1.6384
|-
| 450.0 || 1.8, 3.6
|-
| 460.8 || 1.8432, 3.6864
|-
| 480.0 || 3.84, 1.92
|-
| 491.52 || 3.93216, 1.96608
|-
| 500.0 || 4.0, 2.0, 1.0
|-
| 512.0 || 1.024, 2.048, 4.096
|-
| 532.48 || 1.06496, 2.12992
|-
| 552.96 || 2.21184, 1.10592
|-
| 599.04 || 1.19808, 2.39616
|-
| 600.0 || 1.2, 2.4
|-
| 614.4 || 1.2288, 2.4576
|-
| 625.0 || 1.25, 2.5
|-
| 640.0 || 2.56, 1.28
|-
| 655.36 || 1.31072, 2.62144
|-
| 665.6 || 1.3312, 2.6624
|-
| 720.0 || 1.44, 2.88
|-
| 737.28 || 1.47456, 2.94912
|-
| 750.0 || 1.5, 3.0
|-
| 768.0 || 1.536, 3.072
|-
| 798.72 || 3.19488, 1.59744
|-
| 800.0 || 1.6, 3.2
|-
| 819.2 || 3.2768, 1.6384
|-
| 840.0 || 1.68, 3.36
|-
| 860.16 || 3.44064, 1.72032
|-
| 875.0 || 3.5, 1.75
|-
| 896.0 || 3.584, 1.792
|-
| 900.0 || 1.8, 3.6
|-
| 921.6 || 1.8432, 3.6864
|-
| 931.84 || 1.86368, 3.72736
|-
| 960.0 || 3.84, 1.92
|-
| 983.04 || 1.96608, 3.93216
|-
| 998.4 || 3.9936, 1.9968
|-
| 1000.0 || 4.0, 2.0
|-
| 1024.0 || 4.096, 2.048
|-
| 1050.0 || 2.1
|-
| 1064.96 || 2.12992
|-
| 1075.2 || 2.1504
|-
| 1080.0 || 2.16
|-
| 1105.92 || 2.21184
|-
| 1120.0 || 2.24
|-
| 1125.0 || 2.25
|-
| 1146.88 || 2.29376
|-
| 1152.0 || 2.304
|-
| 1198.08 || 2.39616
|-
| 1200.0 || 2.4
|-
| 1228.8 || 2.4576
|-
| 1280.0 || 2.56
|-
| 1290.24 || 2.58048
|-
| 1310.72 || 2.62144
|-
| 1331.2 || 2.6624
|-
| 1350.0 || 2.7
|-
| 1382.4 || 2.7648
|-
| 1397.76 || 2.79552
|-
| 1400.0 || 2.8
|-
| 1433.6 || 2.8672
|-
| 1440.0 || 2.88
|-
| 1474.56 || 2.94912
|-
| 1500.0 || 3.0
|-
| 1536.0 || 3.072
|-
| 1600.0 || 3.2
|-
| 1625.0 || 3.25
|-
| 1638.4 || 3.2768
|-
| 1650.0 || 3.3
|-
| 1658.88 || 3.31776
|-
| 1664.0 || 3.328
|-
| 1680.0 || 3.36
|-
| 1689.6 || 3.3792
|-
| 1720.32 || 3.44064
|-
| 1730.56 || 3.46112
|-
| 1750.0 || 3.5
|-
| 1760.0 || 3.52
|-
| 1792.0 || 3.584
|-
| 1797.12 || 3.59424
|-
| 1800.0 || 3.6
|-
| 1802.24 || 3.60448
|-
| 1843.2 || 3.6864
|-
| 1863.68 || 3.72736
|-
| 1875.0 || 3.75
|-
| 1920.0 || 3.84
|-
| 1950.0 || 3.9
|-
| 1966.08 || 3.93216
|-
| 1996.8 || 3.9936
|-
| 2000.0 || 4.0
|-
| 2027.52 || 4.05504
|-
| 2048.0 || 4.096
|}

<span id="X440-supported-dual-rates"></span>
== X440 Supported Master Clock Rate combinations (Dual Rate) ==
<b>Important:</b> For the best RF performance it is required to configure the master clock rate that is connected to the higher RF-ADC/DAC converter rate on the first radio and the MCR connected to the lower converter rate second. Not all master clock rate combinations listed in this table will comply to this requirement by themselves. Specifying the converter_rate argument or swapping the master clock rates will help resolving issues. The selected FPGA bitfile may further limit the maximum supported master clock rate.
{| class="wikitable" style="text-align: center; margin:auto"
|-
| MCR0 (MHz) || MCR1 (MHz)
|-
| 125.0 || 250.0, 375.0, 500.0, 750.0, 875.0, 1000.0, 1125.0, 1625.0, 1750.0, 1875.0, 2000.0
|-
| 128.0 || 384.0, 512.0, 768.0, 1152.0
|-
| 133.12 || 266.24, 399.36, 532.48, 665.6, 798.72, 931.84, 1064.96, 1198.08, 1331.2, 1730.56, 1863.68, 1996.8
|-
| 150.0 || 300.0, 450.0, 600.0, 750.0, 900.0, 1050.0, 1350.0, 1500.0, 1650.0, 1800.0, 1950.0
|-
| 153.6 || 307.2, 614.4, 1228.8
|-
| 160.0 || 320.0, 640.0, 800.0, 1120.0, 1280.0, 1600.0, 1760.0
|-
| 163.84 || 327.68, 655.36, 1146.88, 1310.72, 1474.56, 1802.24
|-
| 184.32 || 368.64, 552.96, 737.28, 1105.92, 1290.24, 1474.56, 1658.88, 1843.2, 2027.52
|-
| 199.68 || 399.36, 599.04, 798.72, 998.4, 1198.08, 1397.76, 1797.12, 1996.8
|-
| 200.0 || 400.0, 800.0, 1200.0, 1400.0, 1600.0
|-
| 204.8 || 409.6, 819.2, 1433.6, 1638.4
|-
| 240.0 || 360.0, 480.0, 600.0, 720.0, 840.0, 960.0, 1440.0, 1680.0, 1800.0, 1920.0
|-
| 245.76 || 491.52, 860.16, 983.04, 1720.32, 1966.08
|-
| 250.0 || 125.0, 375.0, 500.0, 750.0, 875.0, 1000.0, 1500.0, 1625.0, 1750.0, 1875.0, 2000.0
|-
| 256.0 || 640.0, 896.0, 1024.0, 1280.0, 1664.0, 1792.0, 2048.0
|-
| 266.24 || 133.12, 399.36, 532.48, 665.6, 798.72, 931.84, 1064.96, 1331.2, 1730.56, 1863.68, 1996.8
|-
| 300.0 || 150.0, 450.0, 600.0, 750.0, 900.0, 1050.0, 1500.0, 1650.0, 1800.0, 1950.0
|-
| 307.2 || 153.6, 614.4, 1228.8
|-
| 320.0 || 160.0, 640.0, 800.0, 1120.0, 1280.0, 1600.0, 1760.0
|-
| 327.68 || 163.84, 655.36, 1146.88, 1310.72, 1802.24
|-
| 360.0 || 240.0, 600.0, 720.0, 1080.0, 1800.0
|-
| 368.64 || 184.32, 552.96, 737.28, 1105.92, 1290.24, 1474.56, 1658.88, 1843.2, 2027.52
|-
| 375.0 || 125.0, 250.0, 750.0, 1125.0, 1500.0, 1875.0
|-
| 384.0 || 128.0, 768.0, 1152.0, 1536.0
|-
| 399.36 || 133.12, 199.68, 266.24, 599.04, 665.6, 798.72, 998.4, 1198.08, 1331.2, 1397.76, 1797.12, 1996.8
|-
| 400.0 || 200.0, 800.0, 1200.0, 1400.0, 1600.0
|-
| 409.6 || 204.8, 819.2, 1433.6, 1638.4
|-
| 450.0 || 150.0, 300.0, 600.0, 750.0, 900.0, 1350.0, 1500.0, 1800.0
|-
| 460.8 || 768.0, 921.6, 1075.2, 1382.4, 1536.0
|-
| 480.0 || 240.0, 720.0, 840.0, 960.0, 1440.0, 1680.0, 1920.0
|-
| 491.52 || 245.76, 860.16, 983.04, 1720.32, 1966.08
|-
| 500.0 || 125.0, 250.0, 750.0, 875.0, 1000.0, 1500.0, 1750.0, 2000.0
|-
| 512.0 || 128.0, 768.0, 1536.0
|-
| 532.48 || 133.12, 266.24, 798.72, 931.84, 1064.96, 1331.2, 1863.68
|-
| 552.96 || 184.32, 368.64, 737.28, 1105.92, 1290.24, 1474.56, 1658.88, 1843.2
|-
| 599.04 || 199.68, 399.36, 798.72, 998.4, 1198.08, 1397.76, 1797.12, 1996.8
|-
| 600.0 || 150.0, 240.0, 300.0, 360.0, 450.0, 720.0, 900.0, 1000.0, 1050.0, 1500.0, 1800.0, 2000.0
|-
| 614.4 || 153.6, 307.2, 1228.8
|-
| 640.0 || 160.0, 256.0, 320.0, 800.0, 1120.0, 1280.0, 1600.0
|-
| 655.36 || 163.84, 327.68, 1146.88, 1310.72
|-
| 665.6 || 133.12, 266.24, 399.36, 798.72, 1331.2, 1996.8
|-
| 720.0 || 240.0, 360.0, 480.0, 600.0, 960.0, 1440.0, 1680.0, 1800.0, 1920.0
|-
| 737.28 || 184.32, 368.64, 552.96, 1105.92, 1290.24, 1474.56, 1843.2
|-
| 750.0 || 125.0, 150.0, 250.0, 300.0, 375.0, 450.0, 500.0, 900.0, 1000.0, 1125.0, 1500.0, 1750.0, 1875.0, 2000.0
|-
| 768.0 || 128.0, 384.0, 460.8, 512.0, 921.6, 1152.0, 1536.0
|-
| 798.72 || 133.12, 199.68, 266.24, 399.36, 532.48, 599.04, 665.6, 998.4, 1064.96, 1198.08, 1331.2, 1397.76, 1863.68, 1996.8
|-
| 800.0 || 160.0, 200.0, 320.0, 400.0, 640.0, 1200.0, 1400.0, 1600.0
|-
| 819.2 || 204.8, 409.6, 1433.6, 1638.4
|-
| 840.0 || 240.0, 480.0, 1680.0
|-
| 860.16 || 245.76, 491.52, 1720.32
|-
| 875.0 || 125.0, 250.0, 500.0, 1750.0
|-
| 896.0 || 256.0, 1792.0
|-
| 900.0 || 150.0, 300.0, 450.0, 600.0, 750.0, 1500.0, 1800.0
|-
| 921.6 || 460.8, 768.0, 1536.0
|-
| 931.84 || 133.12, 266.24, 532.48, 1863.68
|-
| 960.0 || 240.0, 480.0, 720.0, 1440.0, 1920.0
|-
| 983.04 || 245.76, 491.52, 1966.08
|-
| 998.4 || 199.68, 399.36, 599.04, 798.72, 1198.08, 1996.8
|-
| 1000.0 || 125.0, 250.0, 500.0, 600.0, 750.0, 1500.0, 2000.0
|-
| 1024.0 || 256.0, 1280.0, 2048.0
|-
| 1050.0 || 150.0, 300.0, 600.0
|-
| 1064.96 || 133.12, 266.24, 532.48, 798.72, 1331.2
|-
| 1075.2 || 460.8
|-
| 1080.0 || 360.0
|-
| 1105.92 || 184.32, 368.64, 552.96, 737.28, 1474.56, 1658.88, 1843.2
|-
| 1120.0 || 160.0, 320.0, 640.0
|-
| 1125.0 || 125.0, 375.0, 750.0, 1500.0, 1875.0
|-
| 1146.88 || 163.84, 327.68, 655.36
|-
| 1152.0 || 128.0, 384.0, 768.0, 1536.0
|-
| 1198.08 || 133.12, 199.68, 399.36, 599.04, 798.72, 998.4, 1797.12, 1996.8
|-
| 1200.0 || 200.0, 400.0, 800.0, 1600.0
|-
| 1228.8 || 153.6, 307.2, 614.4
|-
| 1280.0 || 160.0, 256.0, 320.0, 640.0, 1024.0, 1600.0
|-
| 1290.24 || 184.32, 368.64, 552.96, 737.28
|-
| 1310.72 || 163.84, 327.68, 655.36
|-
| 1331.2 || 133.12, 266.24, 399.36, 532.48, 665.6, 798.72, 1064.96, 1996.8
|-
| 1350.0 || 150.0, 450.0
|-
| 1382.4 || 460.8
|-
| 1397.76 || 199.68, 399.36, 599.04, 798.72
|-
| 1400.0 || 200.0, 400.0, 800.0
|-
| 1433.6 || 204.8, 409.6, 819.2
|-
| 1440.0 || 240.0, 480.0, 720.0, 960.0, 1920.0
|-
| 1474.56 || 163.84, 184.32, 368.64, 552.96, 737.28, 1105.92
|-
| 1500.0 || 150.0, 250.0, 300.0, 375.0, 450.0, 500.0, 600.0, 750.0, 900.0, 1000.0, 1125.0, 2000.0
|-
| 1536.0 || 384.0, 460.8, 512.0, 768.0, 921.6, 1152.0
|-
| 1600.0 || 160.0, 200.0, 320.0, 400.0, 640.0, 800.0, 1200.0, 1280.0
|-
| 1625.0 || 125.0, 250.0
|-
| 1638.4 || 204.8, 409.6, 819.2
|-
| 1650.0 || 150.0, 300.0
|-
| 1658.88 || 184.32, 368.64, 552.96, 1105.92
|-
| 1664.0 || 256.0
|-
| 1680.0 || 240.0, 480.0, 720.0, 840.0
|-
| 1720.32 || 245.76, 491.52, 860.16
|-
| 1730.56 || 133.12, 266.24
|-
| 1750.0 || 125.0, 250.0, 500.0, 750.0, 875.0
|-
| 1760.0 || 160.0, 320.0
|-
| 1792.0 || 256.0, 896.0
|-
| 1797.12 || 199.68, 399.36, 599.04, 1198.08
|-
| 1800.0 || 150.0, 240.0, 300.0, 360.0, 450.0, 600.0, 720.0, 900.0
|-
| 1802.24 || 163.84, 327.68
|-
| 1843.2 || 184.32, 368.64, 552.96, 737.28, 1105.92
|-
| 1863.68 || 133.12, 266.24, 532.48, 798.72, 931.84
|-
| 1875.0 || 125.0, 250.0, 375.0, 750.0, 1125.0
|-
| 1920.0 || 240.0, 480.0, 720.0, 960.0, 1440.0
|-
| 1950.0 || 150.0, 300.0
|-
| 1966.08 || 245.76, 491.52, 983.04
|-
| 1996.8 || 133.12, 199.68, 266.24, 399.36, 599.04, 665.6, 798.72, 998.4, 1198.08, 1331.2
|-
| 2000.0 || 125.0, 250.0, 500.0, 600.0, 750.0, 1000.0, 1500.0
|-
| 2027.52 || 184.32, 368.64
|-
| 2048.0 || 256.0, 1024.0
|}

<span id="references"></span>
== References and Related Documentation ==
* [https://www.ni.com/en/solutions/aerospace-defense/radar-electronic-warfare-sigint/advantages-of-direct-rf-sampling-architectures.html Advantages of Direct RF Sampling Architectures]
* [https://docs.xilinx.com/r/en-US/pg269-rf-data-converter Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)]
* [https://events.gnuradio.org/event/21/contributions/392/attachments/123/285/Lo%20and%20behold,%20no%20LO.pdf GRcon 23 - Lo and behold, no LO!]
* [https://docs.xilinx.com/r/en-US/ds926-zynq-ultrascale-plus-rfsoc/RF-ADC-Electrical-Characteristics Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)]

= Footnotes =
<references />