Debugging FPGA images - Revision history

NicolasCuervo: /* Overview */

2017-12-29T17:40:21Z

‎Overview

NicolasCuervo: /* Save the project and finish Synthesis */

2017-07-11T20:44:38Z

‎Save the project and finish Synthesis

NicolasCuervo at 11:18, 16 December 2016

2016-12-16T11:18:45Z

NicolasCuervo at 15:16, 3 December 2016

2016-12-03T15:16:20Z

NicolasCuervo: /* External references */

2016-12-02T09:28:24Z

‎External references

NicolasCuervo: /* Overview */

2016-12-02T09:27:27Z

‎Overview

NicolasCuervo: /* Overview */

2016-12-02T09:23:47Z

‎Overview

NicolasCuervo: /* Revision History */

2016-11-30T19:57:24Z

‎Revision History

NicolasCuervo at 19:56, 30 November 2016

2016-11-30T19:56:21Z

Show changes

NicolasCuervo at 17:34, 6 October 2016

2016-10-06T17:34:22Z

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 But how about debugging your HDL code? This comes really handy when you want to follow closely the behavior of your signals within your hardware design. This Application Note will follow the basic steps needed to create a "chipscope image", which allow you to use the Vivado GUI visual tools to debug your design.
-Before we start, this App note assumes that you have been working already with some fpga code and you want to debug it. Being this the case, we assume that you have UHD installed, the FPGA repository cloned, the right version of Xilinx Vivado installed (by the moment this is being written we use Vivado 2015.4) and its environment initialized. If not, we assume you are familiar on how to do the previously noted procedures.
+Before we start, this App note assumes that you have been working already with some FPGA code and you want to debug it. Being this the case, we assume that you have UHD installed, the FPGA repository cloned, the right version of Xilinx Vivado installed (by the moment this is being written we use Vivado 2015.4) and its environment initialized. If not, we assume you are familiar on how to do the previously noted procedures.
 For illustration purposes, here we are going to check the status of some of the output signals of one of the RFNoC blocks we currently provide. However, the same procedure can be used to check the status of any signal within your hardware code, being input, output, or intermediate signal, and being the code a core description, a module for your library or your custom RFNoC block.

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 For this test in particular you are going to need to have a DDC (Digital down converter) in addition to the UUT for visualization purposes on a host. To add this blocks into the bitstream, go to  <syntaxhighlight lang="bash" enclose="none">{fpga-repository}/[usrp3|usrp3_rfnoc/tools/scripts/</syntaxhighlight> and inside that directory run the following command:
-     $ ./make.py siggen ddc -g
+     $ ./uhd_image_builder.py siggen ddc -g
-This will set up your Vivado environment and start the build of an FPGA image with the signal generator and the DDC blocks. The option '-g' is telling the script that at some point during the build process the Vivado User Interface should be opened, as it is where we are going to set up our debug image. For  <syntaxhighlight lang="bash" enclose="none">make.py</syntaxhighlight> usage and options please refer to  the [[Getting_Started_with_RFNoC_Development#Wiring_up_computation_engines_and_building_the_FPGA image|Wiring up computation engines and building the FPGA image]] section of our getting started guide, or simply run  <syntaxhighlight lang="bash" enclose="none">make.py --help in your terminal</syntaxhighlight>
+This will set up your Vivado environment and start the build of an FPGA image with the signal generator and the DDC blocks. The option '-g' is telling the script that at some point during the build process the Vivado User Interface should be opened, as it is where we are going to set up our debug image. For  <syntaxhighlight lang="bash" enclose="none">uhd_image_builder.py</syntaxhighlight> usage and options please refer to  the [[Getting_Started_with_RFNoC_Development#Wiring_up_computation_engines_and_building_the_FPGA image|Wiring up computation engines and building the FPGA image]] section of our getting started guide, or simply run  <syntaxhighlight lang="bash" enclose="none">uhd_image_builder.py --help in your terminal</syntaxhighlight>
 '''Note: ''' ''The FPGA image building process may take over an hour.''
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 '''Note: ''' Most of the time Vivado will auto-detect your highest hierarchy module, but it may happen that it just slips to it and then it will ask you which it. If this happens, you can select the verilog file according to the target device that you are chipscoping as the top module (e.g. x300.v or e300.v)
 Now wait until the synthesis is finished. This won't take long, and after it finishes a window will prompted saying that the synthesis is done, and asking if you want to run the implementation. Click on cancel, as we need to setup the debugging parameters first.
 == Setup debug ==

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 = Application Note Number =
-'''AN-XXX'''
+'''AN-121'''
 = Revision History =
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 |style="text-align:center;"| Initial creation
 |}
 = Abstract =
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      |   |   |   * DDC_0
-which tells us that the blocks '''Signal Generator, DUC and DDC''' were correctly added into the device. Keep in mind that the DmA FIFO and two instances of the radio are added by default into an X310 device. Now, go back to the Vivado GUI and click on "Refres
+which tells us that the blocks '''Signal Generator, DUC and DDC''' were correctly added into the device. Keep in mind that the DmA FIFO and two instances of the radio are added by default into an X310 device. Now, go back to the Vivado GUI and click on "Refresh device" right on the top of the Vivado Window. After that, your debugging signals should appear and you are ready to start chipscoping.
-  #WIP
+If you have come successfully until this point, then you can play around with the signals and checking the result in the debugging panel or, even better, apply this technique to debug your own RFNoC design!
 = External references =

@@ Line 9: / Line 9: @@
 |-
 |style="text-align:center;"| 2016-11-28
-|style="text-align:center;"| Nicolas Cuervo
+|style="text-align:center;"| Nicolas Cuervo <br> Sugandha Gupta
 |style="text-align:center;"| Initial creation
 |}
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 * '''Vivado (version 2015.4): ''' As stated in the overview, you'll be working directly with HDL code that you need to build and synthesize. Depending on your target device, you may even need a non-free license (which is the case for the X3XX devices). In the case of Ettus' embedded devices, you can proceed with your design using the Vivado Webpack.
 = Choosing your signals =
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 = Running the debug bitstream in the target device =
-   #TODO
+   #WIP
 = External references =

← Older revision		Revision as of 09:28, 2 December 2016
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	[7] [https://www.xilinx.com/support/documentation/ip_documentation/ila/v3_0/pg172-ila.pdf LogiCORE IP Integrated Logic Analyzer v3.0]		[7] [https://www.xilinx.com/support/documentation/ip_documentation/ila/v3_0/pg172-ila.pdf LogiCORE IP Integrated Logic Analyzer v3.0]
		+
		+	[8] [https://www.xilinx.com/support/documentation/application_notes/xapp199.pdf Xilinx AN - Writing efficient Testbenches]

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 For illustration purposes, here we are going to check the status of some of the output signals of one of the RFNoC blocks we currently provide. However, the same procedure can be used to check the status of any signal within your hardware code, being input, output, or intermediate signal, and being the code a core description, a module for your library or your custom RFNoC block.
-''' Note: ''' Keep in mind that this procedure intends to probe the signals in a fully designed block, which has been also built into a FPGA .bit file and is running in a supported device. This is *not* intended to be a way to test directly your designed code, as building an FPGA image may take several minutes (even hours). For small functionality checks, we strongly recommend you to write a testbench for your code, which will allow you to have more iterations without the need of building and synthesizing your hardware description. You can follow the [https://files.ettus.com/manual/md_usrp3_sim_writing_testbenches.html - Writing Testbenches] section of our reference manual to have insights on how to write your own testbench.
+''' Note: ''' Keep in mind that this procedure intends to probe the signals in a fully designed block, which has been also built into a FPGA .bit file and is running in a supported device. This is *not* intended to be a way to test directly your designed code, as building an FPGA image may take several minutes (even hours). For small functionality checks, we strongly recommend you to write a testbench for your code, which will allow you to have more iterations without the need of building and synthesizing your hardware description. You can follow the [https://files.ettus.com/manual/md_usrp3_sim_writing_testbenches.html - Writing Testbenches] section of our reference manual to have insights on how to write your own testbench. In addition, there is plenty of online resources (such as [8]) that provide enough information to get you started with your simulation.
 = Prerequisites =

← Older revision		Revision as of 17:34, 6 October 2016
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−	When you are developing your own application, you might come to the point on which you'd like to build an FPGA image for your USRP. You might want to modify part of the cores, add some custom functionality, or even add your custom RFNoC block! For that you might follow tutorials such as the [[Getting_Started_with_RFNoC_Development#Building the FPGA image\|Building the FPGA image]] section of one our "getting started" guides.	+	When you are developing your own application, you might come to the point on which you would like to build an FPGA image for your USRP. You might want to modify part of the cores, add some custom functionality, or even add your custom RFNoC block! For that you might follow tutorials such as the [[Getting_Started_with_RFNoC_Development#Building the FPGA image\|Building the FPGA image]] section of one our "getting started" guides.

	But how about debugging your HDL code? This comes really handy when you want to follow closely the behaviour of your signals within your hardware design. This Application Note will follow the basic steps needed to create a "chipscope image", which allow you to use the Vivado GUI visual tools to debug your design.		But how about debugging your HDL code? This comes really handy when you want to follow closely the behaviour of your signals within your hardware design. This Application Note will follow the basic steps needed to create a "chipscope image", which allow you to use the Vivado GUI visual tools to debug your design.
		+
		+	Before we start, this App note assumes that you have been working already with some fpga code and you want to debug it. Being this the case, we assume that you have UHD installed, the FPGA repository cloned, the right version of Xilinx Vivado installed (by the moment this is being written we use Vivado 2015.4) and its environment initialized. If not, we assume you are familiar on how to do the previously noted procedures.
		+
		+	For illustration purposes, here we are going to check the status of some of the output signals of one of the RFNoC blocks we currently provide. However, the sane procedure can be used to check the status of any signal within your hardware code, being input, output, or intermediate signal, and being the code a core description, a module for your library or your custom RFNoC block.