RFNoC (UHD 3.0) - Revision history

MartinBraun: MartinBraun moved page RFNoC to RFNoC (UHD 3.0)

2022-02-07T15:27:32Z

MartinBraun moved page RFNoC to RFNoC (UHD 3.0)

Ettus: /* Blocks Included with Default FPGA Images */

2019-07-31T17:56:41Z

‎Blocks Included with Default FPGA Images

Ettus: /* Supported Devices */

2019-07-31T17:49:19Z

‎Supported Devices

MichaelDickens: /* RFNoC Resources */ Fix "sigcom 2013 Paper" link to use "https"

2019-05-20T19:17:48Z

‎RFNoC Resources: Fix "sigcom 2013 Paper" link to use "https"

MichaelDickens: Fix link for "Virginia Tech Presentation - RFNoC Deep Dive: FPGA"

2019-05-20T19:15:24Z

Fix link for "Virginia Tech Presentation - RFNoC Deep Dive: FPGA"

MichaelDickens: Fix link for "Virginia Tech Presentation - RFNoC Deep Dive: Host Side"

2019-05-20T19:14:11Z

Fix link for "Virginia Tech Presentation - RFNoC Deep Dive: Host Side"

MichaelDickens: Fix link/document for "Virginia Tech Presentation - Introduction to RFNoC"

2019-05-20T19:12:17Z

Fix link/document for "Virginia Tech Presentation - Introduction to RFNoC"

Ettus: /* Overview */

2018-06-27T14:19:22Z

‎Overview

Ettus at 19:07, 13 April 2017

2017-04-13T19:07:45Z

Ettus: /* Overview */

2017-03-29T20:47:19Z

‎Overview

@@ Line 38: / Line 38: @@
 *OFDM: Burst detection + synchronization, equalizer, packet demodulator
 *and [https://github.com/EttusResearch/fpga/tree/maint/usrp3/lib/rfnoc more...]
 ==RFNoC FAQs==

@@ Line 22: / Line 22: @@
 ==Supported Devices==
 * E310/E312
 * X300/X310
 ==Sample of Available Blocks==

@@ Line 193: / Line 193: @@
 *[https://kb.ettus.com/images/1/1e/RFNoC_Wireless_at_VirginiaTech_2014_Host.pdf Virginia Tech Presentation - RFNoC Deep Dive: Host Side]
 *[https://kb.ettus.com/images/7/78/RFNoC_Wireless_at_VirginiaTech_2014_FPGA.pdf Virginia Tech Presentation - RFNoC Deep Dive: FPGA]
-*[http://conferences.sigcomm.org/sigcomm/2013/papers/srif/p45.pdf sigcom 2013 Paper]
+*[https://conferences.sigcomm.org/sigcomm/2013/papers/srif/p45.pdf sigcom 2013 Paper]
 [[Category:Software Resources]]

@@ Line 192: / Line 192: @@
 *[https://kb.ettus.com/images/e/eb/RFNoC_Wireless_at_VirginiaTech_2014_Intro.pdf Virginia Tech Presentation - Introduction to RFNoC]
 *[https://kb.ettus.com/images/1/1e/RFNoC_Wireless_at_VirginiaTech_2014_Host.pdf Virginia Tech Presentation - RFNoC Deep Dive: Host Side]
-*[http://www.ettus.com/content/files/RFNoC_Wireless_at_VT_FPGA.pdf Virginia Tech Presentation - RFNoC Deep Dive: FPGA]
+*[https://kb.ettus.com/images/7/78/RFNoC_Wireless_at_VirginiaTech_2014_FPGA.pdf Virginia Tech Presentation - RFNoC Deep Dive: FPGA]
 *[http://conferences.sigcomm.org/sigcomm/2013/papers/srif/p45.pdf sigcom 2013 Paper]
 [[Category:Software Resources]]

@@ Line 191: / Line 191: @@
 *[https://www.youtube.com/watch?v=8cPd3t88djE Virginia Tech Video Presentation]
 *[https://kb.ettus.com/images/e/eb/RFNoC_Wireless_at_VirginiaTech_2014_Intro.pdf Virginia Tech Presentation - Introduction to RFNoC]
-*[http://www.ettus.com/content/files/RFNoC_Wireless_at_VT_Host.pdf Virginia Tech Presentation - RFNoC Deep Dive: Host Side]
+*[https://kb.ettus.com/images/1/1e/RFNoC_Wireless_at_VirginiaTech_2014_Host.pdf Virginia Tech Presentation - RFNoC Deep Dive: Host Side]
 *[http://www.ettus.com/content/files/RFNoC_Wireless_at_VT_FPGA.pdf Virginia Tech Presentation - RFNoC Deep Dive: FPGA]
 *[http://conferences.sigcomm.org/sigcomm/2013/papers/srif/p45.pdf sigcom 2013 Paper]
 [[Category:Software Resources]]

← Older revision	Revision as of 15:27, 7 February 2022
(No difference)

@@ Line 7: / Line 7: @@
 We are quickly building out the library of ready-to-use RFNoC blocks and already have many available, including the blocks necessary for an OFDM stack (e.g., detection, synchronization, equalizer, packet demodulator).
-RFNoC is integrated with the UHD™ software, and all USRP devices from the third-generation on (X300 Series, E300 Series) are supported by RFNoC out-of-the-box. Like UHD, RFNoC is also Free and Open Source Software, and the full source code can be found in our public code repositories.
+RFNoC is integrated with the UHD™ software, and all USRP devices from the third-generation on (X300 Series, E300 Series) are supported by RFNoC out-of-the-box. Like UHD, RFNoC is also Free and Open Source Software (LGPL), and the full source code can be found in our public code repositories.
 ||[[File:rfnoc.png|250px]]
 |}

← Older revision		Revision as of 19:07, 13 April 2017
Line 182:		Line 182:

	https://www.xilinx.com/support/answers/60510.html		https://www.xilinx.com/support/answers/60510.html
		+
		+	==Licensing==
		+	* [[Licensing FAQ]]

	==RFNoC Resources==		==RFNoC Resources==

@@ Line 1: / Line 1: @@
 ==Overview==
 {|
-|style="vertical-align:top; width: 60%;"|RFNoC is a network-distributed heterogeneous processing tool with a focus on enabling FPGA processing in USRP devices. It allows you to move data on and off of an FPGA in a transparent way, thus enabling seamless use of both host-based and FPGA-based processing in an application. The result is a much simpler way to leverage FPGA processing capabilities and IP in your application which can scale across multiple FPGAs and devices across a network.
+|style="vertical-align:top; width: 60%;"|RFNoC is a network-distributed heterogeneous processing tool with a focus on enabling FPGA processing in USRP devices. It allows you to move data on and off of an FPGA in a transparent way, thus enabling seamless use of both host-based and FPGA-based processing in an application. It provides a way to leverage FPGA processing capabilities and IP in your application which can scale across multiple FPGAs and devices across a network.
 Signal processing algorithms are contained modules known as "Computation Engines" or "RFNoC Blocks", and an interface wrapper is provided to encapsulate existing or external IP to use with RFNoC. This allows you to import Xilinx™ CoreGen™ IP blocks, for example, and use them immediately in your RFNoC application. The internals of a RFNoC block are wholly independent from any other block, and can be designed with any tool that supports AXI stream interfaces, including VHDL, Verilog, and Xilinx™ Vivado™ HLS.