Synchronizing USRP Events Using Timed Commands in UHD - Revision history

JonathonPendlum: Make example clearer by showing that the set_rx_freq() call has a channel parameter

2025-12-27T07:29:29Z

Make example clearer by showing that the set_rx_freq() call has a channel parameter

2025-08-26T09:32:26Z

Extended FPGA table to include B206mini

2020-04-17T12:56:27Z

make the history a comment; please keep it updated!)

2020-03-06T18:38:36Z

‎A System-Level Example

2020-03-06T18:34:45Z

‎A System-Level Example

2020-03-02T03:45:43Z

‎Application Note Number

2020-03-02T03:44:25Z

‎Revision History

2020-03-02T03:41:16Z

‎Example: Using Timed Commands to Control GPIO

2020-03-02T03:39:10Z

‎Example: Using Timed Commands to Control GPIO

2020-03-02T02:40:41Z

‎Example: Using Timed Commands to Control GPIO

@@ Line 70: / Line 70: @@
   uhd::tune_request_t tune_request(freq);
-  usrp->set_rx_freq(tune_request);
+  usrp->set_rx_freq(tune_request, channel); // Call once per channel
   std::this_thread::sleep_for(std::chrono::milliseconds(110)); //sleep 110ms (~10ms after retune occurs) to allow LO to lock

@@ Line 191: / Line 191: @@
 |-
-|B210/B205mini
+|B210/B205mini/B206mini
 |Xilinx Spartan 6 XC6SLX150
 |8

@@ Line 1: / Line 1: @@
 ==Application Note Number==
 '''AN-883'''
+<!-- Internal use only: please do keep this updated!
 ==Revision History==
 {| class="wikitable"
@@ Line 12: / Line 12: @@
 |style="text-align:center;"| Initial creation
 |}
 ==Abstract==

← Older revision		Revision as of 18:38, 6 March 2020
Line 90:		Line 90:

	Our system will begin to stream data 1s after the time returned by <code>usrp->get_time_now()</code>. Data sent to the host will be phase coherent between the 4 RX channels in this system. This architecture allows a system with X310 + UBX daughterboards to maintain a known phase relationship between channels across runs of code and system power cycles.		Our system will begin to stream data 1s after the time returned by <code>usrp->get_time_now()</code>. Data sent to the host will be phase coherent between the 4 RX channels in this system. This architecture allows a system with X310 + UBX daughterboards to maintain a known phase relationship between channels across runs of code and system power cycles.
		+
		+	For more detail, see [https://files.ettus.com/manual/page_sync.html USRP Manual: Device Synchronization]

	==Clocking and Timekeeping in the USRP==		==Clocking and Timekeeping in the USRP==

@@ Line 74: / Line 74: @@
   usrp->clear_command_time();
-With the above code block, we are able to set a command time equal to the current time + 1s. Any commands that are called after <code>set_command_time()</code> will be sent to the USRP with a timestamp corresponding to the argument passed to <code>set_command_time()</code>. Because of this timestamp, the USRP will wait until the command time passes to execute the tune request. This will ensure that the LO and DSP chain of our USRPs are retuned synchronously (on the same clock cycle), satisfying the third requirement for phase coherent operation.
+With the above code block, we are able to set a command time equal to the current time + 0.1s. Any commands that are called after <code>set_command_time()</code> will be sent to the USRP with a timestamp corresponding to the argument passed to <code>set_command_time()</code>. Because of this timestamp, the USRP will wait until the command time passes to execute the tune request. This will ensure that the LO and DSP chain of our USRPs are retuned synchronously (on the same clock cycle), satisfying the third requirement for phase coherent operation.
 The final step in configuring our system is to set up synchronous streaming from both radios. For this example, we'll set up synchronous RX streaming using the following code:

@@ Line 8: / Line 8: @@
 !Details
 |-
-|style="text-align:center;"| 2020-02-10
+|style="text-align:center;"| 2020-03-1
 |style="text-align:center;"| Sam Reiter
 |style="text-align:center;"| Initial creation

@@ Line 338: / Line 338: @@
      uint32_t all_zero = 0x00;
-     // reset usrp time to 0.0s
+     // reset usrp time to 0.00
      usrp->set_time_source("internal");
      usrp->set_time_next_pps(uhd::time_spec_t(0.0));
      std::this_thread::sleep_for(std::chrono::milliseconds(2000));
-     uhd::time_spec_t now_time = usrp->get_time_last_pps();
+     uhd::time_spec_t now_time = usrp->get_time_last_pps();        // define t=0
      // set gpio pins up for output

@@ Line 348: / Line 348: @@
      usrp->set_gpio_attr("FP0", "DDR", all_one, gpio_line, 0);
      usrp->set_gpio_attr("FP0", "CTRL", all_zero, gpio_line, 0);
-     usrp->set_gpio_attr("FP0", "OUT", all_one, gpio_line, 0);
+     usrp->set_gpio_attr("FP0", "OUT", all_one, gpio_line, 0);     // reset HIGH (async)
      // set all gpio lines to output 0
      usrp->clear_command_time();
      usrp->set_command_time(now_time + uhd::time_spec_t(2.0));
-     usrp->set_gpio_attr("FP0", "OUT", all_zero, gpio_line, 0);
+     usrp->set_gpio_attr("FP0", "OUT", all_zero, gpio_line, 0);    // set LOW @ t=2
      // set all gpio lines to output 1
      usrp->clear_command_time();
      usrp->set_command_time(now_time + uhd::time_spec_t(4.0));
-     usrp->set_gpio_attr("FP0", "OUT", all_one, gpio_line, 0);
+     usrp->set_gpio_attr("FP0", "OUT", all_one, gpio_line, 0);    // set HIGH @ t=4
      // set all gpio lines to output 0
      usrp->clear_command_time();
      usrp->set_command_time(now_time + uhd::time_spec_t(6.0));
-     usrp->set_gpio_attr("FP0", "OUT", all_zero, gpio_line, 0);
+     usrp->set_gpio_attr("FP0", "OUT", all_zero, gpio_line, 0);   // set LOW @ t=6
      usrp->clear_command_time();

@@ Line 334: / Line 334: @@
      // set up some catch-all masks
-     uint32_t gpio_line = 0xF; // only the bottom 4 lines: 0xF = 00001111 = Pin 0, 1, 2, $ 3
+     uint32_t gpio_line = 0xF; // only the bottom 4 lines: 0xF = 00001111 = Pin 0, 1, 2, 3
      uint32_t all_one = 0xFF;
      uint32_t all_zero = 0x00;