Using the RFNoC Replay Block in UHD 4 - Revision history

WadeFife: Add notes specific to E31x devices.

2022-07-15T17:10:24Z

Add notes specific to E31x devices.

WadeFife: WadeFife moved page Using the RFNoC Replay Block 4 to Using the RFNoC Replay Block in UHD 4

2022-03-23T17:38:08Z

WadeFife moved page Using the RFNoC Replay Block 4 to Using the RFNoC Replay Block in UHD 4

MartinBraun at 16:10, 1 March 2022

2022-03-01T16:10:08Z

MartinBraun at 12:19, 1 March 2022

2022-03-01T12:19:04Z

MartinBraun: /* Building the FPGA */

2022-03-01T12:16:31Z

‎Building the FPGA

MartinBraun at 12:12, 1 March 2022

2022-03-01T12:12:51Z

MartinBraun: MartinBraun moved page Using the RFNoC Replay Block 4.0 to Using the RFNoC Replay Block 4

2022-03-01T11:54:53Z

MartinBraun moved page Using the RFNoC Replay Block 4.0 to Using the RFNoC Replay Block 4

WadeFife: Minor edits, formatting changes

2022-02-25T22:02:43Z

Minor edits, formatting changes

MartinBraun at 15:19, 7 February 2022

2022-02-07T15:19:16Z

MartinBraun: /* Building the FPGA */

2022-02-04T13:43:12Z

‎Building the FPGA

@@ Line 8: / Line 8: @@
 the USRP X410, X310/X300, N300/N310/N320 and E320 devices. For UHD 3.x, please
 refer to [[Using_the_RFNoC_Replay_Block|the UHD 3.x replay block Application Note]].
 An introduction to RFNoC with UHD 4.0 and above can be found [[Getting_Started_with_RFNoC_in_UHD_4.0|here]].
@@ Line 422: / Line 426: @@
      rfnoc_image_builder -y x310_replay_image_core.yml [ --fpga-dir ~/usr/uhd/fpga ]
 This will create a bitfile that contains the replay block. It can be loaded onto

@@ Line 298: / Line 298: @@
 There are two memory alignment values that need to be considered when dealing
 with the replay block. The first is the word size, which is the minimum number of
-bytes per DRAM transaction. For all default configurations, the word size is 64 bits,
+bytes per DRAM transaction. For most configurations, the word size is 64 bits,
 which means that only even numbers of samples can be recorded or played back
 when using 16-bit complex samples (at 4 bytes per sample). Use the <code>get_word_size()</code>
-API call to identify the correct word size.
+API call to identify the correct word size. The word size can go up to 512 bits.
 The second alignment value is the memory's page boundaries. The start addresses
-for record and replay must fall onto a 4 kiB memory boundary to ensure correct
+for record and replay should fall onto a 4 kiB memory boundary to ensure correct
 alignment of data.

@@ Line 100: / Line 100: @@
 If your device does not report a replay block, then you need to load
-an FPGA image which includes this block. See ... for instructions on how to do
+an FPGA image which includes this block. See [[#building_fpga|this section]] for instructions on how to do
 this before you proceed. If it does report a block, you can move to the next
 section.
@@ Line 307: / Line 307: @@
 alignment of data.
 ==Building Custom FPGA Images with a Replay Block==
 ===Configure the Default Shell===
@@ Line 338: / Line 340: @@
 default install location of <code>/opt/Xilinx/Vivado</code>.
-<span id="building_fpga">==Building the FPGA==</span>
+===Building the FPGA===
-−
 '''Note:''' Most bitfiles already include the replay block! This section is

@@ Line 338: / Line 338: @@
 default install location of <code>/opt/Xilinx/Vivado</code>.
-==Building the FPGA==
+<span id="building_fpga">==Building the FPGA==</span>
 '''Note:''' Most bitfiles already include the replay block! This section is

@@ Line 30: / Line 30: @@
      uhd_usrp_probe --args <device args>
 Depending on your device, the output could look like this (truncated):
@@ Line 95: / Line 99: @@
 this is a four-port replay block.
-If your device does not report a replay block, then you need to build and load
+If your device does not report a replay block, then you need to load
 an FPGA image which includes this block. See ... for instructions on how to do
 this before you proceed. If it does report a block, you can move to the next
@@ Line 195: / Line 199: @@
 '''Note:''' The amount of memory available to the Replay block is limited by the
 size of the DRAM on the USRP and how the memory interface is configured on the USRP.
-For example, the <code>axi_intercon_2x64_128_bd</code> IP used by the X310 is
+By default, we expose the entire memory of the device, but it is possible to modify
-configured to give each connected device an address space of 32&nbsp;MiB. As a
+<code>axi_intercon_2x64_128_bd</code> if less memory should be made accessible.
-result, the Replay block will be limited to this amount of memory. The
-<code>axi_intercon_2x64_128_bd</code> file must be modified if more than 32&nbsp;MiB needs to be buffered.
+Devices have the following amount of memory:
 To restart recording from the same offset, the following API call can be used:
@@ Line 239: / Line 262: @@
      uhd::stream_cmd_t stream_cmd(uhd::stream_cmd_t::STREAM_MODE_START_CONTINUOUS);
      stream_cmd.stream_now = true;
      replay_ctrl->issue_stream_cmd(stream_cmd, replay_chan);
@@ Line 252: / Line 274: @@
 <code>STREAM_MODE_START_CONTINUOUS</code> causes playback to continue indefinitely
 until explicitly stopped. <code>STREAM_MODE_NUM_SAMPS_AND_DONE</code> causes only
-the specified number of samples to be played once. The <code>num_samps</code>
+the specified number of samples to be played once. Playback can be stopped by issuing
-parameter is a 28-bit value, limiting this mode of playback to 2<sup>28</sup>
+ a stop command.
-words at a time. Playback can be stopped by issuing a stop command.
      stream_cmd.stream_mode = uhd::stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS;
@@ Line 318: / Line 339: @@
 ==Building the FPGA==
 In order to use the Replay block, it must be built into the FPGA image for the
@@ Line 366: / Line 391: @@
 As you can see, the replay block requires configuration in up to four sections:
 * For maximum flexibility, every port of the replay block will receive its own stream endpoint. This is not a requirement of the replay block, but allows its flexible use.
-* Of course, the block needs to be declared in the <code>noc_blocks</code> section.
+* Of course, the block needs to be declared in the <code>noc_blocks</code> section. The blocks contain two parameters, NUM_PORTS, and MEM_ADDR_W. The former is the number of ports this RFNoC block may have. The latter is the width of the memory address word, i.e., it is log2(memory_size).
 * It must be connected to the stream endpoints in the <code>connections</code> section, as well as to the DRAM banks (BSP connection).
 * Finally, the clock domain needs to be connected.
 When the YAML image core file is complete, save it, e.g., as x310_replay_image_core.yml,
 and pass it to the image builder:
-     rfnoc_image_builder -y x310_replay_image_core.yml
+     rfnoc_image_builder -y x310_replay_image_core.yml [ --fpga-dir ~/usr/uhd/fpga ]
 This will create a bitfile that contains the replay block. It can be loaded onto

← Older revision	Revision as of 17:38, 23 March 2022
(No difference)

← Older revision	Revision as of 11:54, 1 March 2022
(No difference)

@@ Line 159: / Line 159: @@
 for <code>rfnoc_replay_samples_from_file</code> may be considered an example
 for best practices on how to use the replay block.
 ==Using the Replay Block==
@@ Line 221: / Line 220: @@
          std::this_thread::sleep_for(100ms);
-===Playing back Data===
+===Playing Back Data===
 Prior to playing back recorded data, it is necessary to configure the base
@@ Line 274: / Line 273: @@
 the block on playback is tagged with this timestamp.
+===Memory Alignment and Word Sizes===
-===Memory alignment and word sizes===
 There are two memory alignment values that need to be considered when dealing
 with the replay block. The first is the word size, which is the minimum number of
-bytes per transaction. For all default configurations, the word size is 64 bits,
+bytes per DRAM transaction. For all default configurations, the word size is 64 bits,
 which means that only even numbers of samples can be recorded or played back
 when using 16-bit complex samples (at 4 bytes per sample). Use the <code>get_word_size()</code>
@@ Line 287: / Line 285: @@
 for record and replay must fall onto a 4 kiB memory boundary to ensure correct
 alignment of data.
 ==Building Custom FPGA Images with a Replay Block==
@@ Line 308: / Line 305: @@
 For the rest of the Application Note, we assume the repository was cloned into
-the location ~/src/uhd.
+the location <code>~/src/uhd</code>.
 ===Installing the FPGA Tools===
@@ Line 349: / Line 346: @@
          parameters:
            NUM_PORTS: 2
-     connections:
+    connections:
        # ...connections for all the other blocks...
        # ep4 to replay0(0)
@@ Line 361: / Line 359: @@
        - { srcblk: replay0, srcport: out_1, dstblk: ep5,     dstport: in0  }
        # BSP Connections
-       - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }     MEM_ADDR_W: 30
+       - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
      clk_domains:
-        # ...all other clock domains...
+      # ...all other clock domains...
-        - { srcblk: _device_, srcport: dram,  dstblk: replay0, dstport: mem  }
+      - { srcblk: _device_, srcport: dram,  dstblk: replay0, dstport: mem  }
 As you can see, the replay block requires configuration in up to four sections:

@@ Line 340: / Line 340: @@
          data: True                      # Endpoint passes data traffic
          buff_size: 4096                 # Ingress buffer size for data
-−
      noc_blocks:
        # ... all the other blocks...