X300/X310 - Revision history

DylanCaswell: /* X3xx */

2025-03-20T21:49:05Z

‎X3xx

DylanCaswell: /* X3xx */

2025-03-20T21:47:50Z

‎X3xx

MichaelDickens: /* Ref Clock - 10 MHz */ remove "sinusoidal" while we determine the correct path via internal testing

2024-10-01T16:43:29Z

‎Ref Clock - 10 MHz: remove "sinusoidal" while we determine the correct path via internal testing

JonathonPendlum: Fix missing link in FAQ for programming FPGA

2023-10-27T21:01:14Z

Fix missing link in FAQ for programming FPGA

MichaelDickens: /* Certificate of Volatility */ add link to NI website

2023-08-14T17:16:22Z

‎Certificate of Volatility: add link to NI website

WanLiu at 18:06, 7 July 2023

2023-07-07T18:06:28Z

MartinBraun: /* FPGA */

2022-07-13T16:03:38Z

‎FPGA

MichaelDickens: /* Guidance on SFP+ Adapters for Fiber Connectivity on USRP X300/X310 */ fix links

2021-04-14T14:42:37Z

‎Guidance on SFP+ Adapters for Fiber Connectivity on USRP X300/X310: fix links

MichaelDickens: /* Option: USRP X300/X310 Rackmount */

2020-05-01T13:20:21Z

‎Option: USRP X300/X310 Rackmount

MichaelDickens: /* Option: USRP X300/X310 Rackmount */ tweak wording

2020-05-01T13:13:38Z

‎Option: USRP X300/X310 Rackmount: tweak wording

@@ Line 91: / Line 91: @@
 * [[Media:cu x3xx motherboard cca.stp.gz| Motherboard Version 1]]
-* [[Media:cu x3xx motherboard cca2.stp| Motherboard Version 2, updated March 2025]]
+* [https://kb.ettus.com/images/0/03/cu_x3xx_motherboard_cca2.stp Motherboard Version 2, updated March 2025]
 ====X3xx Enclosure====

@@ Line 89: / Line 89: @@
 ===CAD/STP Models===
 ====X3xx====
-* [[Media:cu x3xx motherboard cca.stp.gz| Motherboard]]
+* [[Media:cu x3xx motherboard cca.stp.gz| Motherboard Version 1]]
 ====X3xx Enclosure====

@@ Line 376: / Line 376: @@
 ===Ref Clock - 10 MHz===
-Using an external 10 MHz reference clock, a square wave will offer the best phase noise performance, but a sinusoid is acceptable. The power level of the reference clock cannot exceed +15 dBm.
 ===PPS - Pulse Per Second===

@@ Line 798: / Line 798: @@
 * '''How do I update the FPGA images and firmware with the latest from UHD'''
-You can find more information about updating the FPGA image through PCIe, 1/10 GigE, and JTAG here.
+You can find more information about updating the FPGA image in the UHD manual: https://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_getting_started_fpga_update
 * '''How can I modify the FPGA of the USRP X300/X310'''
@@ Line 826: / Line 826: @@
 The USRP X310 includes a larger Kintex-7 series FPGA (XC7K410T) with additional development resources for more complex designs.  The USRP X300 includes the smaller XC7K325T FPGA.
-* '''What is the part number of the X3xx power connector'''
+* '''What is the part number of the X300/X310 power connector'''
 Model: PDP-40 by CUI Inc.
 Power plug connectors for custom power harnesses can be purchased here: https://www.digikey.com/products/en?KeyWords=CP-7340-ND&WT.z_cid=sp_102_buynow
 [[Category:Hardware Resources]]

@@ Line 548: / Line 548: @@
 ==Certificate of Volatility==
-===X300/X310===
-* [[Media:volatility USRP X300 X310 r1.pdf]]
+Found on the [https://www.ni.com/en/support/documentation/product-certifications.html NI Product Certifications lookup tool] [https://www.ni.com/pdf/manuals/377356a.pdf here].
 ==Downloads==

← Older revision		Revision as of 18:06, 7 July 2023
Line 394:		Line 394:

	The +3.3V is for ESD clamping purposes only and not designed to deliver high currents.		The +3.3V is for ESD clamping purposes only and not designed to deliver high currents.
		+
		+	The switching speed is below 10 MHz.

	\| style="vertical-align:top" \| [[File:x3x0 gpio conn.png]]		\| style="vertical-align:top" \| [[File:x3x0 gpio conn.png]]

@@ Line 297: / Line 297: @@
 ===FPGA User Modifications===
 The Verilog code for the FPGA in the USRP X300 and USRP X310 is open-source, and users are free to modify and customize it for their needs. However, certain modifications may result in either bricking the device, or even in physical damage to the unit. Specifically, changing the I/O interface of the FPGA in any way (do not remove any of the I/O for the PCIe interface, such as <code>x300_pcie_int</code> and <code>LvFpga_Chinch_Interface</code>), or modifying the pin and timing constraint files, could result in physical damage to other components on the motherboard, external to the FPGA, and doing this will void the warranty. Also, even if the PCIe interface is not being used, you cannot remove or reassign these pins in the constraint file. The constraint files should not be modified. Please note that modifications to the FPGA are made at the risk of the user, and may not be covered by the warranty of the device.
 ==Interfaces and Connectivity==

@@ Line 728: / Line 728: @@
 ===Known-Good Adapters===
-* [http://approvedoptics.com/blade-networks-bn-ckm-sp-sr/ Approved Optics BN-CKM-SP-SR-A]
+* [https://approvedoptics.com/blade-networks-bn-ckm-sp-sr/ Approved Optics Blade Networks BN-CKM-SP-SR-A]
 ===Known-Good Cables===
-* [http://www.colfaxdirect.com/store/pc/viewPrd.asp?idproduct=1696 Elpeus 10GbE SFP+ AOC Cable, 3 meters]
+* [https://www.colfaxdirect.com/store/pc/viewPrd.asp?idproduct=995&idcategory=2 Myricom Fiber Cables for 10GBase-SR, 3 Meters 10G-SR-3M]
 ==Guidance on 10Gb SFP+ to RJ45 Adapters==

@@ Line 715: / Line 715: @@
 ==Option: USRP X300/X310 Rackmount==
-The USRP X300/X310 was designed to be used with a [https://www.ettus.com/all-products/rackmount-1u/ 1U Rackmount Assembly] for building high-density MIMO systems in a compact and well-organized setup. This mount supports one or two X300/X310 USRPs, and if two are mounted then there are rubber standoffs between the USRPs to avoid both direct contact and surface scratching. If the user will be developing in a laboratory environment or building a high-channel count USRP X300/X310 system, then the 1U Rackmount Assembly is highly recommended. This specific mount is compatible with the USRP X300 and USRP X310 only, and allows the integration of four bidirectional -- or eight receive -- RF channels per 1U.
+The USRP X300 and X310 were designed to be used with a [https://www.ettus.com/all-products/rackmount-1u/ 1U Rackmount Assembly] for building high-density MIMO systems in a compact and well-organized setup. This mount supports one or two compatible USRPs, and if two are mounted then there are rubber standoffs between the USRPs to avoid both direct contact and surface scratching. If the user will be developing in a laboratory environment or building a high-channel count USRP system, then a 1U Rackmount Assembly is highly recommended. This specific mount is compatible with only the USRP X300 and X310, and allows the integration of up to four bidirectional -- or eight receive-only -- RF channels per 1U.
 ==Guidance on SFP+ Adapters for Fiber Connectivity on USRP X300/X310==