Debugging FPGA images
From Ettus Knowledge Base
Revision as of 21:06, 21 September 2016 by NicolasCuervo (Talk | contribs) (Created page with "When you are developing your own application, you might come to the point on which you'd like to build an FPGA image for your USRP. You might want to modify part of the cores,...")
When you are developing your own application, you might come to the point on which you'd like to build an FPGA image for your USRP. You might want to modify part of the cores, add some custom functionality, or even add your custom RFNoC block! For that you might follow tutorials such as the Building the FPGA image section of one our "getting started" guides.
But how about debugging your HDL code? This comes really handy when you want to follow closely the behaviour of your signals within your hardware design. This Application Note will follow the basic steps needed to create a "chipscope image", which allow you to use the Vivado GUI visual tools to debug your design.
