Using the RFNoC Replay Block
Application Note Number
|2018-10-05||Wade Fife||Initial creation|
This application note guides a user through basic use of the RFNoC Replay block and explains how to run the UHD Replay example. This example covers use on the X310 and N310 products.
The Replay block is an RFNoC block that allows recording and playback of arbitrary data using the USRP hardware's DRAM as a buffer. In order to be used, the Replay block must be instantiated in the design and connected to the DRAM. It can take the place of a DMA FIFO or be used concert with a DMA FIFO. In this note we will be replacing the DMA FIFO block with the Replay block and running a UHD example that records data to DRAM from a file then plays it back over the radio repeatedly.
Cloning the Repository
Your system must be configured for RFNoC development to compile and use the RFNoC examples. Here we briefly explain how to setup a system to build and run the RFNoC Replay examples.
Note: Refer to Application Note AN-823 Getting Started with RFNoC Development for a more detailed overview of RFNoC development.
To begin, use these
git clone commands to download the needed UHD and FPGA branches.
Note: At the time of writing, the FPGA code is included in UHD-3.13 and later, but the UHD example is not yet included in any releases. So for this application note we will use the master branches.
$ git clone https://github.com/EttusResearch/uhd.git $ git clone https://github.com/EttusResearch/fpga.git
If UHD and/or FPGA are already installed, it would be sufficient to checkout the branches mentioned and update them them (
git pull) then rebuild UHD.
Building and Installing UHD
If you have not already done so, follow the steps in Application Note AN-445 under Update and Install dependencies.
Note: Refer to Application Note AN-445 for detailed instructions on building and installing UHD from the source code. However, RFNOC must be enabled when running CMake in order to run the RFNoC examples. The instructions below summarize the basic steps required to run the Replay example.
To build and install UHD, begin by opening a terminal in the UHD repository that you cloned, then create a
build folder within the
host host folder of the repository.
$ cd uhd/host $ mkdir build $ cd build
Run CMake with RFNoC enabled to create the Makefiles.
$ cmake -DENABLE_RFNOC=ON ../
Run Make with RFNOC enabled to build UHD with RFNoC support.
Install UHD, using the default install prefix, which will install UHD under the /usr/local/lib folder. You need to run this as root due to the permissions on that folder.
$ sudo make install
Update the system's shared library cache.
$ sudo ldconfig
Make sure that the
LD_LIBRARY_PATH environment variable is defined and includes the folder under which UHD was installed. Most commonly, you can add the line below to the end of your
$HOME/.bashrc file. (Note: the
LD_LIBRARY_PATH location may vary depending on your Linux distribution.
$ export LD_LIBRARY_PATH=/usr/local/lib
Installing FPGA Tools
In order to build the FPGA image for the intended USRP product, you will need to have the Xilinx development tools installed. The specific version required depends on the branch and state of the FPGA code. The UHD-3.13 branches require Vivado 17.4. Refer to the installation instructions for Vivado in order to install these tools. It is recommended that you use the default install location of
/opt/Xilinx/Vivado to ensure compatibility with the FPGA build flow.
Building the FPGA
In order to use the Replay block, it must be built into the FPGA image for the USRP you plan to use. This is currently a manual step. The instructions below are for the X310, but similar instructions apply to the N310.
First, we must modify the Verilog code to include the Replay Block. To do this, modify the file
fpga/top/x300/x300_core.v and change localparam
USE_REPLAY from 0 to 1. This changes the FPGA to instantiate
noc_block_replay instead of
noc_block_axi_dma_fifo. Note that the DMA FIFO will not be included in this example and therefore can not be used.
Note: If using the N310, modify the file
fpga/top/n3xx/n3xx_core.v and make the same change. Other products that support RFNoC can also use the replay block. However, currently, the Replay block must be manually instantiated in the code.
After making the required code change, you are ready to rebuild the FPGA image. Begin by setting up the environment to use the FPGA build tools.
$ cd fpga/usrp3/top/x300 $ source ./setup.sh
Run make to build the desired FPGA image. For example, for the X310 HG image, use could use the following command:
$ make X310_HG
Once compilation is complete, download the image to your USRP X310 product. For example, if the X310 HG image is connected to the 1 Gigabit Ethernet port using the default IP address, then you would run the following command.
$ uhd_image_loader --args="type=x300,addr=192.168.10.2" --fpga-path=./build-X310_HG/x300.bit
After the download has completed, power cycle the X310 to load the new bitstream. Confirm that the Replay block appears in the system by running
$ uhd_usrp_probe --args="addr=192.168.10.2" ..................
Building the Replay Example
In this section we will compile the replay_from_file UHD example.