Difference between revisions of "N200/N210"

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== Device Overview ==
 
== Device Overview ==
 +
 
The USRP Network Series offers high-bandwidth, high-dynamic range processing capability. The Gigabit Ethernet interface of the USRP Network Series allows high-speed streaming capability up to 50 MS/s in both directions (8-bit samples). These features, combined with plug-and-play MIMO capability make the USRP Network an ideal candidate for software defined radio systems with demanding performance requirements.
 
The USRP Network Series offers high-bandwidth, high-dynamic range processing capability. The Gigabit Ethernet interface of the USRP Network Series allows high-speed streaming capability up to 50 MS/s in both directions (8-bit samples). These features, combined with plug-and-play MIMO capability make the USRP Network an ideal candidate for software defined radio systems with demanding performance requirements.
  
 
== Key Features==
 
== Key Features==
 +
 
===N200===
 
===N200===
−
* Xilinx® Spartan® 3A-DSP 1800 FPGA
+
 
−
* 14 bit 100 MS/s dual ADC
+
{|
−
* 16 bit 400 MS/s dual DAC
+
|style="vertical-align:top"|
−
* Frequency range: DC - 6 GHz with suitable daughterboard
+
*50 MHz of RF bandwidth with 8 bit samples
−
* Up to 50 MS/s in both directions
+
*25 MHz of RF bandwidth with 16 bit samples
−
* Full duplex, SISO (1 Tx & 1 Rx)
+
*Gigabit Ethernet connectivity
−
* Fully-Coherent MIMO Capability
+
*MIMO capable - requires two or more USRP N200 devices as motherboard has one daughterboard slot (1 RX + 1 TX connectors)
−
* Optional GPSDO
+
*Onboard FPGA processing
−
* Gigabit Ethernet connectivity
+
*FPGA: Xilinx® Spartan® 3A-DSP XC3SD1800A
 +
*ADCs: 14-bits 100 MS/s
 +
*DACs: 16-bits 400 MS/s
 +
*Ability to lock to external 5 or 10 MHz clock reference
 +
*TCXO Frequency Reference (~2.5ppm)
 +
*Optional internal GPS locked reference oscillator
 +
*FPGA code can be changed with Xilinx® ISE® WebPACK™ tools
 +
*Frequency range: DC - 6 GHz with suitable daughterboard
 +
|[[File:Product n200.jpg|250px|center]]
 +
|}
  
 
===N210===
 
===N210===
−
* Xilinx® Spartan® 3A-DSP 3400 FPGA
+
 
−
* 14 bit 100 MS/s dual ADC
+
{|
−
* 16 bit 400 MS/s dual DAC
+
|style="vertical-align:top"|
−
* Frequency range: DC - 6 GHz with suitable daughterboard
+
*50 MHz of RF bandwidth with 8 bit samples
−
* Up to 50 MS/s in both directions
+
*25 MHz of RF bandwidth with 16 bit samples
−
* Full duplex, SISO (1 Tx & 1 Rx)
+
*Gigabit Ethernet connectivity
−
* Fully-Coherent MIMO Capability
+
*MIMO capable - requires two or more USRP N210 devices as motherboard has one daughterboard slot (1 RX + 1 TX connectors)
−
* Optional GPSDO
+
*Onboard FPGA processing
−
* Gigabit Ethernet connectivity
+
*FPGA: Xilinx® Spartan® 3A-DSP XC3SD3400A
 +
*ADCs: 14-bits 100 MS/s
 +
*DACs: 16-bits 400 MS/s
 +
*Ability to lock to external 5 or 10 MHz clock reference
 +
*TCXO Frequency Reference (~2.5ppm)
 +
*Optional internal GPS locked reference oscillator
 +
*FPGA code can only be changed with the paid version of the Xilinx® ISE® Design Suite tools
 +
*Frequency range: DC - 6 GHz with suitable daughterboard
 +
|[[File:Product n210.jpg|250px|center]]
 +
|}
  
 
==Compatible Daughterboards==
 
==Compatible Daughterboards==
 +
 
* SBX-40
 
* SBX-40
 
* UBX-40
 
* UBX-40
Line 32: Line 53:
 
* LFRX / LFTX
 
* LFRX / LFTX
 
* BasicRX / BasicTX
 
* BasicRX / BasicTX
−
* TVRX2
+
* DBSRX2 (EOL)
−
* DBSRX2
+
* RFX Series (EOL)
 +
* TVRX2 (EOL)
  
 
==RF Specifications==
 
==RF Specifications==
−
===RF Performance (with WBX)===
+
 
 +
===RF Performance Data (with WBX)===
 +
 
 
* SSB/LO Suppression -35/50 dBc
 
* SSB/LO Suppression -35/50 dBc
 
* Phase Noise 1.8 GHz 10kHz -80 dBc/Hz
 
* Phase Noise 1.8 GHz 10kHz -80 dBc/Hz
Line 45: Line 69:
 
* Typical Noise Figure 5 dB
 
* Typical Noise Figure 5 dB
  
−
==Clocks and Samples Rates==
+
==Hardware Specifications==
−
* FIXME NEEL
+
 
 +
* Ettus Research recommends to always use the latest stable version of UHD
 +
 
 +
===N200===
 +
 
 +
* Current Hardware Revision: 4
 +
* Minimum version of UHD required: 3.8.0
 +
 
 +
===N210===
 +
 
 +
* Current Hardware Revision: 4
 +
* Minimum version of UHD required: 3.8.0
  
 
==Physical Specifications==
 
==Physical Specifications==
  
 
===Dimensions===
 
===Dimensions===
 +
 
22 x 16 x 5 cm
 
22 x 16 x 5 cm
 +
 +
===Weight===
 +
 +
1.2 kg
 +
 +
===Drawings===
 +
 +
* [[File:cu usrp-n2x0 motherboard.pdf]]
 +
* [[File:cu ettus-usrp-n2x0.pdf]]
 +
 +
===CAD/STP Models===
 +
 +
====N2xx====
 +
 +
* [[Media:cu usrp-n2x0 motherboard.stp.gz| Motherboard]]
 +
 +
====N2xx Enclosure====
 +
 +
* [[Media:cu ettus-usrp-n2x0.stp.gz|Enclosure]]
  
 
==Environmental Specifications==
 
==Environmental Specifications==
 +
 
===Operating Temperature Range===
 
===Operating Temperature Range===
−
* N200/N210 0-40 °C
+
 
 +
* N200/N210: 25 °C
 +
 
 +
===Operating Humidity Range===
 +
 
 +
* 10% to 90% non-condensing
  
 
==Schematics==
 
==Schematics==
 +
 
===N200/N210===
 
===N200/N210===
 +
 
[http://files.ettus.com/schematics/n200/n2xx.pdf N200/N210 Schematics]
 
[http://files.ettus.com/schematics/n200/n2xx.pdf N200/N210 Schematics]
  
−
==Datasheets==
+
==Key Component Datasheets==
−
* Dual Channel, 16-Bit DAC - [http://www.analog.com/media/en/technical-documentation/data-sheets/AD9777.pdf AD9777]
+
  
−
* Dual Channel, 14-Bit ADC - [http://www.ti.com/lit/ds/symlink/ads62p45.pdf ADS62P4X]
+
{| class="wikitable" style="width:80%"
 +
!Part Number
 +
!Description
 +
!Schematic ID (Page)
 +
|-
 +
|[http://www.analog.com/media/en/technical-documentation/data-sheets/AD9777.pdf AD9777]
 +
|Dual Channel, 16-Bit DAC
 +
|U3 (1)
 +
|-
 +
|[http://www.ti.com/lit/ds/symlink/ads62p45.pdf ADS62P4X]
 +
|Dual Channel, 14-Bit ADC
 +
|U2 (1)
 +
|-
 +
|[http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf XC3SD3400AFG676]
 +
|FPGA
 +
|U1 (2,8,9,10,11,12)
 +
|-
 +
|[http://www.analog.com/media/en/technical-documentation/data-sheets/AD9510.pdf AD9510]
 +
|Clock Distribution IC
 +
|U9 (4)
 +
|-
 +
|[http://download.siliconexpert.com/pdfs/2008/04/26/isys/lsi/ds06-161gphy_et1011c_09-28-2007.pdf ET1011C2]
 +
|Gigabit Ethernet Transceiver
 +
|U12 (6)
 +
|-
 +
|[http://www.cypress.com/file/43236/download CY7C1354C]
 +
|Pipelined SRAM
 +
|U19 (7)
 +
|-
 +
|[http://www.ti.com/lit/ds/symlink/max232.pdf MAX232]
 +
|Drivers/Receiver
 +
|U25 (10)
 +
|-
 +
|}
  
−
* FPGA - [http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf XC3SD3400AFG676] - Double check
+
==FPGA==
  
−
* AD56x3
+
* Utilization statistics are subject to change between UHD releases. This information is current as of UHD 3.9.4 and was taken directly from Xilinx Vivado 2014.4.
  
−
* Clock Distribution IC - [http://www.analog.com/media/en/technical-documentation/data-sheets/AD9510.pdf AD9510]
+
===N200===
  
−
* Gigabit Ethernet Transceiver - [http://download.siliconexpert.com/pdfs/2008/04/26/isys/lsi/ds06-161gphy_et1011c_09-28-2007.pdf ET1011C2]
+
<pre>
 +
Device utilization summary:
 +
---------------------------
  
−
* Pipelined SRAM - [http://www.cypress.com/file/43236/download CY7C1354C]
+
Selected Device : 3sd1800afg676-5
  
−
* Drivers/Receiver [http://www.ti.com/lit/ds/symlink/max232.pdf MAX232]
+
Number of Slices:                    18356  out of  16640  110% (*)
 +
Number of Slice Flip Flops:         20466  out of  33280    61%
 +
Number of 4 input LUTs:              32968  out of  33280    99%
 +
    Number used as logic:            28511
 +
    Number used as Shift registers:    3945
 +
    Number used as RAMs:                512
 +
Number of IOs:                        338
 +
Number of bonded IOBs:                331  out of    519    63%
 +
    IOB Flip Flops:                    342
 +
Number of BRAMs:                        41  out of    84    48%
 +
Number of GCLKs:                        6  out of    24    25%
 +
Number of DCMs:                          1  out of      8    12%
 +
Number of DSP48s:                      31  out of    84    36%
 +
</pre>
  
−
==Mechanical Info==
+
===N210===
  
−
===Weight===
+
<pre>
−
1.2 kg
+
Device utilization summary:
 +
---------------------------
  
−
===Drawings===
+
Selected Device : 3sd3400afg676-5
  
−
==FPGA==
+
Number of Slices:                    18349  out of  23872    76%
−
Lorem ipsum dolor sit amet, consectetur adipisicing elit. Quod voluptates molestias excepturi nisi ea minus hic iste velit optio doloremque similique ab nulla, beatae obcaecati! Nobis, at dolorum id nostrum
+
Number of Slice Flip Flops:          20475  out of  47744    42%
 +
Number of 4 input LUTs:              32986  out of  47744    69%
 +
    Number used as logic:            28529
 +
    Number used as Shift registers:    3945
 +
    Number used as RAMs:                512
 +
Number of IOs:                        338
 +
Number of bonded IOBs:                331  out of    469    70%
 +
    IOB Flip Flops:                    342
 +
Number of BRAMs:                        41  out of    126    32%
 +
Number of GCLKs:                        6  out of    24    25%
 +
Number of DCMs:                          1  out of      8    12%
 +
Number of DSP48s:                      31  out of    126    24%
 +
 
 +
</pre>
  
 
==Interfaces and Connectivity==
 
==Interfaces and Connectivity==
 +
 
===N200/N210===
 
===N200/N210===
 +
 
* Gigabit Ethernet
 
* Gigabit Ethernet
  
 
==Certifications==
 
==Certifications==
 +
 
===RoHS===
 
===RoHS===
 +
 
As of December 1st, 2010 all Ettus Research products are RoHS compliant unless otherwise noted. More information can be found at [http://ettus.com/legal/rohs-information http://ettus.com/legal/rohs-information]
 
As of December 1st, 2010 all Ettus Research products are RoHS compliant unless otherwise noted. More information can be found at [http://ettus.com/legal/rohs-information http://ettus.com/legal/rohs-information]
  
−
==Downloads (FPGA images, E310 images, etc.)==
+
===China RoHS===
−
[http://files.ettus.com/manual/md_fpga.html FPGA Resources]
+
  
−
[http://files.ettus.com/binaries/uhd_stable/ UHD Stable Binaries]
+
'''Management Methods for Controlling Pollution Caused by Electronic Information Products Regulation'''
  
−
[https://github.com/EttusResearch/uhd UHD Source Code on Github]
+
'''Chinese Customers'''
  
 +
National Instruments is in compliance with the Chinese policy on the Restriction of Hazardous Substances (RoHS) used in Electronic Information Products. For more information about the National Instruments China RoHS compliance, visit [http://www.ni.com/environment/rohs_china ni.com/environment/rohs_china].
  
 +
==Letter of Volatility==
  
−
==Application Notes==
+
Found on the [https://www.ni.com/en/support/documentation/product-certifications.html NI Product Certifications lookup tool] [https://www.ni.com/pdf/manuals/377355a.pdf here].
  
 +
==Recovering the N200/N210==
  
−
==FAQ==
+
For a detailed guide to recovering the N200/N210, please see the [[N200/N210 Device Recovery]] application note.
 +
 
 +
==Downloads==
 +
 
 +
[https://files.ettus.com/manual/md_fpga.html FPGA Resources]
 +
 
 +
[https://files.ettus.com/binaries/uhd_stable/ UHD Stable Binaries]
 +
 
 +
[https://github.com/EttusResearch/uhd UHD Source Code on Github]
  
−
[[Category:Product Resource Pages]]
+
[[Category:Hardware Resources]]

Latest revision as of 11:13, 14 August 2023

Device Overview

The USRP Network Series offers high-bandwidth, high-dynamic range processing capability. The Gigabit Ethernet interface of the USRP Network Series allows high-speed streaming capability up to 50 MS/s in both directions (8-bit samples). These features, combined with plug-and-play MIMO capability make the USRP Network an ideal candidate for software defined radio systems with demanding performance requirements.

Key Features

N200

  • 50 MHz of RF bandwidth with 8 bit samples
  • 25 MHz of RF bandwidth with 16 bit samples
  • Gigabit Ethernet connectivity
  • MIMO capable - requires two or more USRP N200 devices as motherboard has one daughterboard slot (1 RX + 1 TX connectors)
  • Onboard FPGA processing
  • FPGA: Xilinx® Spartan® 3A-DSP XC3SD1800A
  • ADCs: 14-bits 100 MS/s
  • DACs: 16-bits 400 MS/s
  • Ability to lock to external 5 or 10 MHz clock reference
  • TCXO Frequency Reference (~2.5ppm)
  • Optional internal GPS locked reference oscillator
  • FPGA code can be changed with Xilinx® ISE® WebPACK™ tools
  • Frequency range: DC - 6 GHz with suitable daughterboard
Product n200.jpg

N210

  • 50 MHz of RF bandwidth with 8 bit samples
  • 25 MHz of RF bandwidth with 16 bit samples
  • Gigabit Ethernet connectivity
  • MIMO capable - requires two or more USRP N210 devices as motherboard has one daughterboard slot (1 RX + 1 TX connectors)
  • Onboard FPGA processing
  • FPGA: Xilinx® Spartan® 3A-DSP XC3SD3400A
  • ADCs: 14-bits 100 MS/s
  • DACs: 16-bits 400 MS/s
  • Ability to lock to external 5 or 10 MHz clock reference
  • TCXO Frequency Reference (~2.5ppm)
  • Optional internal GPS locked reference oscillator
  • FPGA code can only be changed with the paid version of the Xilinx® ISE® Design Suite tools
  • Frequency range: DC - 6 GHz with suitable daughterboard
Product n210.jpg

Compatible Daughterboards

  • SBX-40
  • UBX-40
  • WBX-40
  • CBX-40
  • LFRX / LFTX
  • BasicRX / BasicTX
  • DBSRX2 (EOL)
  • RFX Series (EOL)
  • TVRX2 (EOL)

RF Specifications

RF Performance Data (with WBX)

  • SSB/LO Suppression -35/50 dBc
  • Phase Noise 1.8 GHz 10kHz -80 dBc/Hz
  • Phase Noise 1.8 GHz 100kHz -100 dBc/Hz
  • Phase Noise 1.8 GHz 1MHz -137 dBc/Hz
  • Power Output 15 dBm
  • IIP3 (@ typ NF) 0 dBm
  • Typical Noise Figure 5 dB

Hardware Specifications

  • Ettus Research recommends to always use the latest stable version of UHD

N200

  • Current Hardware Revision: 4
  • Minimum version of UHD required: 3.8.0

N210

  • Current Hardware Revision: 4
  • Minimum version of UHD required: 3.8.0

Physical Specifications

Dimensions

22 x 16 x 5 cm

Weight

1.2 kg

Drawings

CAD/STP Models

N2xx

N2xx Enclosure

Environmental Specifications

Operating Temperature Range

  • N200/N210: 25 °C

Operating Humidity Range

  • 10% to 90% non-condensing

Schematics

N200/N210

N200/N210 Schematics

Key Component Datasheets

Part Number Description Schematic ID (Page)
AD9777 Dual Channel, 16-Bit DAC U3 (1)
ADS62P4X Dual Channel, 14-Bit ADC U2 (1)
XC3SD3400AFG676 FPGA U1 (2,8,9,10,11,12)
AD9510 Clock Distribution IC U9 (4)
ET1011C2 Gigabit Ethernet Transceiver U12 (6)
CY7C1354C Pipelined SRAM U19 (7)
MAX232 Drivers/Receiver U25 (10)

FPGA

  • Utilization statistics are subject to change between UHD releases. This information is current as of UHD 3.9.4 and was taken directly from Xilinx Vivado 2014.4.

N200

Device utilization summary:
---------------------------

Selected Device : 3sd1800afg676-5

 Number of Slices:                    18356  out of  16640   110% (*)
 Number of Slice Flip Flops:          20466  out of  33280    61%
 Number of 4 input LUTs:              32968  out of  33280    99%
    Number used as logic:             28511
    Number used as Shift registers:    3945
    Number used as RAMs:                512
 Number of IOs:                         338
 Number of bonded IOBs:                 331  out of    519    63%
    IOB Flip Flops:                     342
 Number of BRAMs:                        41  out of     84    48%
 Number of GCLKs:                         6  out of     24    25%
 Number of DCMs:                          1  out of      8    12%
 Number of DSP48s:                       31  out of     84    36%

N210

Device utilization summary:
---------------------------

Selected Device : 3sd3400afg676-5

 Number of Slices:                    18349  out of  23872    76%
 Number of Slice Flip Flops:          20475  out of  47744    42%
 Number of 4 input LUTs:              32986  out of  47744    69%
    Number used as logic:             28529
    Number used as Shift registers:    3945
    Number used as RAMs:                512
 Number of IOs:                         338
 Number of bonded IOBs:                 331  out of    469    70%
    IOB Flip Flops:                     342
 Number of BRAMs:                        41  out of    126    32%
 Number of GCLKs:                         6  out of     24    25%
 Number of DCMs:                          1  out of      8    12%
 Number of DSP48s:                       31  out of    126    24%

Interfaces and Connectivity

N200/N210

  • Gigabit Ethernet

Certifications

RoHS

As of December 1st, 2010 all Ettus Research products are RoHS compliant unless otherwise noted. More information can be found at http://ettus.com/legal/rohs-information

China RoHS

Management Methods for Controlling Pollution Caused by Electronic Information Products Regulation

Chinese Customers

National Instruments is in compliance with the Chinese policy on the Restriction of Hazardous Substances (RoHS) used in Electronic Information Products. For more information about the National Instruments China RoHS compliance, visit ni.com/environment/rohs_china.

Letter of Volatility

Found on the NI Product Certifications lookup tool here.

Recovering the N200/N210

For a detailed guide to recovering the N200/N210, please see the N200/N210 Device Recovery application note.

Downloads

FPGA Resources

UHD Stable Binaries

UHD Source Code on Github

Retrieved from "https://kb.ettus.com/index.php?title=N200/N210&oldid=5837"