Difference between revisions of "N200/N210"

From Ettus Knowledge Base
Jump to: navigation, search
(→‎FPGA)
(→‎Key Features)
Line 24: Line 24:
 
* Optional GPSDO
 
* Optional GPSDO
 
* Gigabit Ethernet connectivity
 
* Gigabit Ethernet connectivity
 +
 +
 +
==update==
 +
===USRP N200===
 +
 +
*50 MHz of RF bandwidth with 8 bit samples
 +
*25 MHz of RF bandwidth with 16 bit samples
 +
*Gigabit Ethernet connectivity
 +
*MIMO capable - requires two or more USRP N200 devices as motherboard has one daughterboard slot (1 RX + 1 TX connectors)
 +
*Onboard FPGA processing
 +
*FPGA: Xilinx Spartan XC3SD1800A
 +
*ADCs: 14-bits 100 MS/s
 +
*DACs: 16-bits 400 MS/s
 +
*Ability to lock to external 5 or 10 MHz clock reference
 +
*TCXO Frequency Reference (~2.5ppm)
 +
*Optional internal GPS locked reference oscillator
 +
*FPGA code can be changed with Xilinx® ISE® WebPACK™ tools
 +
 +
===USRP N210===
 +
 +
*50 MHz of RF bandwidth with 8 bit samples
 +
*25 MHz of RF bandwidth with 16 bit samples
 +
*Gigabit Ethernet connectivity
 +
*MIMO capable - requires two or more USRP N210 devices as motherboard has one daughterboard slot (1 RX + 1 TX connectors)
 +
*Onboard FPGA processing
 +
*FPGA: Xilinx Spartan XC3SD3400A
 +
*ADCs: 14-bits 100 MS/s
 +
*DACs: 16-bits 400 MS/s
 +
*Ability to lock to external 5 or 10 MHz clock reference
 +
*TCXO Frequency Reference (~2.5ppm)
 +
*Optional internal GPS locked reference oscillator
 +
*FPGA code can only be changed with the paid version of the Xilinx® ISE® Design Suite tools
  
 
==Compatible Daughterboards==
 
==Compatible Daughterboards==

Revision as of 12:10, 30 April 2016

Device Overview

The USRP Network Series offers high-bandwidth, high-dynamic range processing capability. The Gigabit Ethernet interface of the USRP Network Series allows high-speed streaming capability up to 50 MS/s in both directions (8-bit samples). These features, combined with plug-and-play MIMO capability make the USRP Network an ideal candidate for software defined radio systems with demanding performance requirements.

Key Features

N200

  • Xilinx® Spartan® 3A-DSP 1800 FPGA
  • 14 bit 100 MS/s dual ADC
  • 16 bit 400 MS/s dual DAC
  • Frequency range: DC - 6 GHz with suitable daughterboard
  • Up to 50 MS/s in both directions
  • Full duplex, SISO (1 Tx & 1 Rx)
  • Fully-Coherent MIMO Capability
  • Optional GPSDO
  • Gigabit Ethernet connectivity

N210

  • Xilinx® Spartan® 3A-DSP 3400 FPGA
  • 14 bit 100 MS/s dual ADC
  • 16 bit 400 MS/s dual DAC
  • Frequency range: DC - 6 GHz with suitable daughterboard
  • Up to 50 MS/s in both directions
  • Full duplex, SISO (1 Tx & 1 Rx)
  • Fully-Coherent MIMO Capability
  • Optional GPSDO
  • Gigabit Ethernet connectivity


update

USRP N200

  • 50 MHz of RF bandwidth with 8 bit samples
  • 25 MHz of RF bandwidth with 16 bit samples
  • Gigabit Ethernet connectivity
  • MIMO capable - requires two or more USRP N200 devices as motherboard has one daughterboard slot (1 RX + 1 TX connectors)
  • Onboard FPGA processing
  • FPGA: Xilinx Spartan XC3SD1800A
  • ADCs: 14-bits 100 MS/s
  • DACs: 16-bits 400 MS/s
  • Ability to lock to external 5 or 10 MHz clock reference
  • TCXO Frequency Reference (~2.5ppm)
  • Optional internal GPS locked reference oscillator
  • FPGA code can be changed with Xilinx® ISE® WebPACK™ tools

USRP N210

  • 50 MHz of RF bandwidth with 8 bit samples
  • 25 MHz of RF bandwidth with 16 bit samples
  • Gigabit Ethernet connectivity
  • MIMO capable - requires two or more USRP N210 devices as motherboard has one daughterboard slot (1 RX + 1 TX connectors)
  • Onboard FPGA processing
  • FPGA: Xilinx Spartan XC3SD3400A
  • ADCs: 14-bits 100 MS/s
  • DACs: 16-bits 400 MS/s
  • Ability to lock to external 5 or 10 MHz clock reference
  • TCXO Frequency Reference (~2.5ppm)
  • Optional internal GPS locked reference oscillator
  • FPGA code can only be changed with the paid version of the Xilinx® ISE® Design Suite tools

Compatible Daughterboards

  • SBX-40
  • UBX-40
  • WBX-40
  • CBX-40
  • LFRX / LFTX
  • BasicRX / BasicTX
  • TVRX2
  • DBSRX2

RF Specifications

RF Performance (with WBX)

  • SSB/LO Suppression -35/50 dBc
  • Phase Noise 1.8 GHz 10kHz -80 dBc/Hz
  • Phase Noise 1.8 GHz 100kHz -100 dBc/Hz
  • Phase Noise 1.8 GHz 1MHz -137 dBc/Hz
  • Power Output 15 dBm
  • IIP3 (@ typ NF) 0 dBm
  • Typical Noise Figure 5 dB

Clocks and Samples Rates

  • FIXME NEEL

Physical Specifications

Dimensions

22 x 16 x 5 cm

Environmental Specifications

Operating Temperature Range

  • N200/N210 0-40 °C

Schematics

N200/N210

N200/N210 Schematics

Datasheets

  • Dual Channel, 16-Bit DAC - AD9777
  • AD56x3
  • Clock Distribution IC - AD9510
  • Gigabit Ethernet Transceiver - ET1011C2

Mechanical Info

Weight

1.2 kg

Drawings

FPGA

The available resources on the FPGA will vary depending on the code written for it. Based on the 27 March 2012 FPGA code build, the following resources are available:

USRP N200 (Xilinx Spartan 3A DSP - XC3SD1800A FPGA)

  • General Logic:
    • Flip Flops: 41% free
    • LUTs: 9% free
  • Memory: 52% free
  • DSP Resources: 64% free

USRP N210 (Xilinx Spartan 3A DSP - XC3SD3400A FPGA)

  • General Logic:
    • Flip Flops: 59% free
    • LUTs: 37% free
  • Memory: 68% free
  • DSP Resources: 76% free

Interfaces and Connectivity

N200/N210

  • Gigabit Ethernet

Multiple Device Configuration

  • [ADD]

Certifications

RoHS

As of December 1st, 2010 all Ettus Research products are RoHS compliant unless otherwise noted. More information can be found at http://ettus.com/legal/rohs-information

Certificate of Volatility

  • N200/N210

Downloads (FPGA images, E310 images, etc.)

FPGA Resources

UHD Stable Binaries

UHD Source Code on Github


Application Notes

FAQ

Retrieved from "https://kb.ettus.com/index.php?title=N200/N210&oldid=1488"