Difference between revisions of "RFNoC (UHD 3.0)"
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|style="vertical-align:top; width: 60%;"|Current FPGAs, like the Xilinx Kintex-7 and Zynq-7000 series used in third generation USRP SDRs, have incredible computational capability, but taking advantage of that capability can be difficult when using traditional FPGA design flows. RFNoC is designed to allow you to efficiently harness the full power of the latest generations of FPGAs without being an expert firmware developer. It provides the capability to create FPGA applications as easily as you can create GNU Radio flowgraphs. This includes the ability to seamlessly transfer data to & from an FPGA, from the host PC in your application, dramatically improving the ease of FPGA off-loading. Having a system-level view of the entire SDR application running on both the FPGA and the host PC enables far superior development and debugging. Mixing and matching host-based and FPGA-based processing is transparent to you, and that processing can scale across multiple FPGAs and devices across a network. | |style="vertical-align:top; width: 60%;"|Current FPGAs, like the Xilinx Kintex-7 and Zynq-7000 series used in third generation USRP SDRs, have incredible computational capability, but taking advantage of that capability can be difficult when using traditional FPGA design flows. RFNoC is designed to allow you to efficiently harness the full power of the latest generations of FPGAs without being an expert firmware developer. It provides the capability to create FPGA applications as easily as you can create GNU Radio flowgraphs. This includes the ability to seamlessly transfer data to & from an FPGA, from the host PC in your application, dramatically improving the ease of FPGA off-loading. Having a system-level view of the entire SDR application running on both the FPGA and the host PC enables far superior development and debugging. Mixing and matching host-based and FPGA-based processing is transparent to you, and that processing can scale across multiple FPGAs and devices across a network. | ||
Revision as of 00:04, 11 May 2016
Contents
Overview
| Current FPGAs, like the Xilinx Kintex-7 and Zynq-7000 series used in third generation USRP SDRs, have incredible computational capability, but taking advantage of that capability can be difficult when using traditional FPGA design flows. RFNoC is designed to allow you to efficiently harness the full power of the latest generations of FPGAs without being an expert firmware developer. It provides the capability to create FPGA applications as easily as you can create GNU Radio flowgraphs. This includes the ability to seamlessly transfer data to & from an FPGA, from the host PC in your application, dramatically improving the ease of FPGA off-loading. Having a system-level view of the entire SDR application running on both the FPGA and the host PC enables far superior development and debugging. Mixing and matching host-based and FPGA-based processing is transparent to you, and that processing can scale across multiple FPGAs and devices across a network. | 
|
Supported Devices
- E310/E312
- X300/X310
Key Features
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Available Blocks
- FIFO
- FFT
- FIR
- fosphor (real-time spectrum analyzer)
- Decimator (Keep 1 in N)
- Log Power Calculator
- Radio Interface
- Vector IIR (moving average)
- Window multiplier (for FFT)
- OFDM: Burst detection + synchronization, equalizer, packet demodulator
RFNoC Resources
http://www.ettus.com/blog/2015/06/rfnoc-for-high-performance-sdr
https://github.com/EttusResearch/uhd/wiki/RFNoC:-Getting-Started
https://github.com/EttusResearch/uhd/wiki/RFNoC:--Specification
https://www.youtube.com/watch?v=8cPd3t88djE
http://conferences.sigcomm.org/sigcomm/2013/papers/srif/p45.pdf
http://www-int.etec.uni-karlsruhe.de/seiten/conferences/past/WSR2014/Papers/wsr14_21.pdf
Downloads (FPGA images, E310 images, etc.)
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