Difference between revisions of "N300/N310"

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 +
== Device Overview ==
 +
The USRP N310 is a networked software defined radio that provides reliability and fault-tolerance for deployment in large scale and distributed wireless systems. This device simplifies control and management of a network of radios by introducing the unique capability to remotely perform tasks such as debugging, updating software, rebooting, factory resetting, self-testing, and monitoring system health. The USRP N310 is an all-in-one device that includes two AD9371 transceivers, the Zynq-7100 SoC baseband processor, two SFP+ ports, a built-in GPSDO module, and various other peripheral and synchronization features.
  
 +
== Key Features==
 +
===N310===
 +
{|
 +
|style="vertical-align:top"|
 +
* Xilinx Xilinx Zynq-7100 FPGA SoC
 +
* Dual-core ARM A9 866 MHz CPU
 +
* 4 RX, 4TX in half-wide RU form factor
 +
* 10 MHz – 6 GHz extended frequency range
 +
* Up to 100 MHz of instantaneous bandwidth per channel
 +
* RX, TX filter bank
 +
* 16 bit ADC, 14 bit DAC
 +
* Configurable sample rates: 122.88, 125, and 153.6 MS/s
 +
* Two SFP+ ports (1 GbE, 10 GbE, Aurora)
 +
* RJ45 (1 GbE)
 +
* 10 MHz clock reference
 +
* PPS time reference
 +
* External RX, TX LO input ports
 +
* Built-in GPSDO
 +
* 1 Type A USB host port
 +
* 1 micro-USB port (serial console, JTAG)
 +
* Trusted Platform Module v1.2
 +
* Watchdog timer
 +
* OpenEmbedded Linux
 +
* High channel density
 +
* Reliable and fault-tolerant deployment
 +
* Remote management capability
 +
* Stand-alone operation
 +
 +
|[[File:n310 kit.png|700px|center]]
 +
|}
 +
 +
==RF Specifications==
 +
===Transmitter===
 +
* Number of channels: 4
 +
* Frequency Range: 10 MHz to 6 GHz
 +
* Maximum instantaneous bandwidth: 100 MHz
 +
* Minimum frequency step
 +
** 7.32 Hz @ 122.88 MHz sample rate
 +
** 7.45 Hz @ 125 MHz sample rate
 +
** 9.15 Hz @ 153.6 MHz sample rate
 +
 +
* Maximum output power (P​ out​ ): See Table 1
 +
* Gain range
 +
** -30 dB to 25 dB (10 MHz to 300 MHz)
 +
** -30 dB to 20 dB (300 MHz to 6 GHz)
 +
 +
* Gain step: 1 dB
 +
* Supported I/Q sample rates:
 +
** 122.88 MHz, 125 MHz, 153.6 MHz
 +
 +
* Spurious-free dynamic range (SFDR) > 50 dBc
 +
* Output third-order intercept (OIP3) See Table 2
 +
 +
 +
{| class="wikitable" style="width:80%"
 +
! Frequency
 +
! Maximum Output Power
 +
|-
 +
 +
| 10 MHz to 500 MHz
 +
| +16 dBm
 +
|-
 +
 +
| > 500 MHz to 1 GHz
 +
| +18 dBm
 +
|-
 +
 +
| > 1 GHz to 4 GHz
 +
| +18 dBm
 +
|-
 +
 +
| > 4 GHz to 6 GHz
 +
| +12 dBm
 +
|-
 +
 +
 +
|}
 +
Table 1: Maximum Output Power
 +
 +
{| class="wikitable" style="width:80%"
 +
! Frequency
 +
! Output Third-Order Intercept (IP3)
 +
|-
 +
 +
| 10 MHz to 2 GHz
 +
| > 30 dBm
 +
|-
 +
 +
| > 2 GHz to 4 GHz
 +
| > 20 dBm
 +
|-
 +
 +
| > 4 GHz to 6 GHz
 +
| > 10 dBm
 +
|-
 +
 +
|}
 +
Table 2: Third-Order Intercept (IP3)
 +
 +
 +
===Receiver===
 +
* Number of channels: 4
 +
* Frequency Range: 10 MHz to 6 GHz
 +
* Maximum instantaneous bandwidth: 100 MHz
 +
* Minimum frequency step
 +
** 7.32 Hz @ 122.88 MHz sample rate
 +
** 7.45 Hz @ 125 MHz sample rate
 +
** 9.15 Hz @ 153.6 MHz sample rate
 +
 +
* Gain step: 1
 +
* Maximum recommended input power (P​ in​ ) 1 dB: -15 dBm
 +
 +
* Noise figure: > 50 dBc
 +
* Spurious-free dynamic range (SFDR) See Table 3
 +
 +
* Third-order intermodulation distortion (IMD3) See Table 4
 +
 +
* Supported I/Q sample rates
 +
**122.88 MHz, 125 MHz, 153.6 MHz
 +
 +
 +
 +
{| class="wikitable" style="width:80%"
 +
! Frequency
 +
! RX2 Noise Figure
 +
! TX/RX Noise Figure
 +
|-
 +
 +
|1.8 GHz
 +
|5.8 dB
 +
|6.8 dB
 +
|-
 +
 +
|2.4 GHz to 2.6 GHz
 +
|6.5 dB
 +
|7.5 dB
 +
|-
 +
 +
|3.3 GHz to 4.8 GHz
 +
|5.5 dB
 +
|6.0 dB
 +
|-
 +
 +
|5.0 GHz to 5.8 GHz
 +
|7.0 dB
 +
|7.5 dB
 +
|-
 +
 +
|}
 +
Table 3: Noise Figure
 +
 +
 +
 +
{| class="wikitable" style="width:80%"
 +
!Frequency
 +
!RX IMD3
 +
|-
 +
 +
|0.5 GHz to 3 GHz
 +
|< -80 dBc
 +
|-
 +
 +
|> 3 GHz to 4 GHz
 +
|< -74 dBc
 +
|-
 +
 +
|> 4 GHz to 6 GHz
 +
|< -81 dBc
 +
|-
 +
 +
|}
 +
Table 4: RX Third-Order Intermodulation Distortion (IMD3)
 +
* Noise figure is measured at maximum gain state on receiver signal path.
 +
 +
 +
===Onboard DRAM===
 +
* DDR3 Memory size
 +
** 2,048 MB (PL)
 +
** 1,024 MB (PS)
 +
 +
 +
==Power==
 +
You must use either the Level VI Efficiency power supply provided in the shipping kit, or another UL listed ITE power supply marked ​<code>LPS</code>, with the USRP N310.
 +
 +
* Input voltage: 12 VDC
 +
* Input current:  7.0 A, maximum
 +
* Typical power consumption: 50 W to 80 W, varies by application
 +
 +
==Hardware Specifications==
 +
* Ettus Research recommends to always use the latest stable version of UHD
 +
* If you need to clean the module, wipe it with a dry towel.
 +
 +
===N310===
 +
* Current Hardware Revision: A
 +
* Minimum version of UHD required: 3.11.0.0
 +
 +
==Physical Specifications==
 +
 +
===Dimensions===
 +
====(L × W × H)====
 +
* 35.71 cm × 21.11 cm × 4.37 cm
 +
* 14.06 in. × 8.31 in. × 1.72 in.
 +
 +
===Weight===
 +
* 3.13 kg
 +
 +
==Environmental Specifications==
 +
===Operating Temperature Range===
 +
* N310: 0 to 50 °C
 +
 +
===Storage Temperature Range===
 +
* N310: -40 to 70 °C
 +
 +
===Operating Humidity Range===
 +
* 10% to 90% non-condensing
 +
 +
==Schematics==
 +
===N310===
 +
[http://files.ettus.com/schematics/N300/N310.pdf N310 Schematics]
 +
 +
==GPSDO==
 +
* Support GPSDO NMEA Strings
 +
 +
===Sensors===
 +
You can query the lock status with the <code>gps_locked</code> sensor, as well as obtain raw NMEA sentences using the <code>gps_gprmc</code>, and <code>gps_gpgga</code> sensors. Location information can be parsed out of the <code>gps_gpgga</code> sensor by using <code>gpsd</code> or another NMEA parser.
 +
 +
==FPGA==
 +
===FPGA User Modifications===
 +
The Verilog code for the FPGA in the USRP N300/N310 is open-source, and users are free to modify and customize it for their needs. However, certain modifications may result in either bricking the device, or even in physical damage to the unit. Specifically, changing the I/O interface of the FPGA in any way, or modifying the pin and timing constraint files, could result in physical damage to other components on the motherboard, external to the FPGA, and doing this will void the warranty. Also, even if the PCIe interface is not being used, you cannot remove or reassign these pins in the constraint file. The constraint files should not be modified. Please note that modifications to the FPGA are made at the risk of the user, and may not be covered by the warranty of the device.
 +
 +
==Interfaces and Connectivity==
 +
Follow the links below for additional information on configuring each interface for the USRP N300 or N310 SDRs.
 +
 +
* 100 MS/s Full Duplex @ 16-bit
 +
 +
===Front Panel===
 +
{|
 +
| style="width:50%" |
 +
 +
* '''PWR''': Power switch
 +
 +
* '''RF 0 Group'''
 +
** '''TX/RX SMA/LED''': RF Input Port / Indicates that data is streaming on the TX/RX channel on daughterboard 0, channel 0
 +
** '''RX2 SMA/LED''': RF Input Port / Indicates that data is streaming on the RX2 channel on daughterboard 0, channel 0
 +
 +
* '''RF 1 Group'''
 +
** '''TX/RX SMA/LED''': RF Input Port / Indicates that data is streaming on the TX/RX channel on daughterboard 0, channel 1
 +
** '''RX2 SMA/LED''': RF Input Port / Indicates that data is streaming on the RX2 channel on daughterboard 0, channel 1
 +
 +
* '''RF 2 Group'''
 +
** '''TX/RX SMA/LED''': RF Input Port / Indicates that data is streaming on the TX/RX channel on daughterboard 1, channel 0
 +
** '''RX2 SMA/LED''': RF Input Port / Indicates that data is streaming on the RX2 channel on daughterboard 1, channel 0
 +
 +
* '''RF 3 Group'''
 +
** '''TX/RX SMA/LED''': RF Input Port / Indicates that data is streaming on the TX/RX channel on daughterboard 1, channel 1
 +
** '''RX2 SMA/LED''': RF Input Port / Indicates that data is streaming on the RX2 channel on daughterboard 1, channel 1
 +
 +
* '''LO IN 0/1'''
 +
** '''TX''': Input port for TX LO of Daughterboard 0
 +
** '''RX''': Input port for RX LO of Daughterboard 0
 +
 +
* '''LO IN 2/3'''
 +
** '''TX''': Input port for TX LO of Daughterboard 1
 +
** '''RX''': Input port for RX LO of Daughterboard 1
 +
 +
* '''GPIO'''
 +
** '''GPIO''': DB15 GPIO Interface. Additional details below.
 +
 +
 +
| style="vertical-align:top" | [[File:n310 front.png|700px]]
 +
|}
 +
 +
===Rear Panel===
 +
{|
 +
| style="width:50%" |
 +
* '''GPS ANT''': Connection for the GPS antenna
 +
* '''REF IN''': Reference clock input
 +
* '''PPS/TRIG IN''': Input port for the PPS signal
 +
* '''TRIG OUT''': Output port for the exported reference clock
 +
* '''PWR''': Connector for the USRP N310 Series power supply
 +
 +
* '''RESET''': Input button to reset device
 +
 +
* '''MicroSD''': MicroSD Card for OE Linux File System
 +
* '''JTAG''': Micro USB connector for the on-board USB-JTAG programmer
 +
* '''USB 2.0''': Host USB connector to ARM CPU
 +
* '''SFP+''': 1/10Gb SFP+ ports for Ethernet interfaces
 +
 +
* '''10/1000/1000''': 10/100/1000 Mb Ethernet interface to ARM CPU
 +
 +
| style="vertical-align:top" | [[File:n310 back.png|700px]]
 +
|}
 +
 +
===Ref Clock - 10 MHz===
 +
Using an external 10 MHz reference clock, a square wave will offer the best phase noise performance, but a sinusoid is acceptable. The power level of the reference clock cannot exceed +10 dBm.
 +
 +
===PPS - Pulse Per Second===
 +
Using a PPS signal for timestamp synchronization requires a square wave signal with the following a 5Vpp amplitude.
 +
 +
To test the PPS input, you can use the following tool from the UHD examples:
 +
 +
* <code><args></code> are device address arguments (optional if only one USRP device is on your machine)
 +
 +
    cd <install-path>/lib/uhd/examples ./test_pps_input –args=<args>
 +
 +
 +
===Front Panel GPIO===
 +
{|
 +
| style="width:50%" |
 +
The GPIO port is not meant to drive big loads. You should not try to source more than 5mA per pin.
 +
 +
The +3.3V is for ESD clamping purposes only and not designed to deliver high currents.
 +
 +
|}
 +
 +
 +
====Power on state====
 +
The hardware power on state and UHD initial state for the front-panel GPIOs is high-Z. For the N310, there are no external pull-ups/pull-downs for the GPIO pins, but the FPGAs do have them and they are configured as follows: N310: pull-down.
 +
 +
====Pin Mapping====
 +
* Pin 1: +3.3V
 +
* Pin 2: Data[0]
 +
* Pin 3: Data[1]
 +
* Pin 4: Data[2]
 +
* Pin 5: Data[3]
 +
* Pin 6: Data[4]
 +
* Pin 7: Data[5]
 +
* Pin 8: Data[6]
 +
* Pin 9: Data[7]
 +
* Pin 10: Data[8]
 +
* Pin 11: Data[9]
 +
* Pin 12: Data[10]
 +
* Pin 13: Data[11]
 +
* Pin 14: 0V
 +
* Pin 15: 0V
 +
 +
'''Note''': Please see the [http://files.ettus.com/manual/page_gpio_api.html E3x0/X3x0/N3x0 GPIO API] for information on configuring and using the GPIO bus.
 +
 +
==Certifications==
 +
===RoHS===
 +
As of December 1st, 2010 all Ettus Research products are RoHS compliant unless otherwise noted. More information can be found at [http://ettus.com/legal/rohs-information http://ettus.com/legal/rohs-information]
 +
 +
===China RoHS===
 +
'''Management Methods for Controlling Pollution Caused by Electronic Information Products Regulation'''
 +
 +
'''Chinese Customers'''
 +
 +
National Instruments is in compliance with the Chinese policy on the Restriction of Hazardous Substances (RoHS) used in Electronic Information Products. For more information about the National Instruments China RoHS compliance, visit [http://www.ni.com/environment/rohs_china ni.com/environment/rohs_china].
 +
 +
==Downloads==
 +
[http://files.ettus.com/manual/md_fpga.html FPGA Resources]
 +
 +
[http://files.ettus.com/binaries/uhd_stable/ UHD Stable Binaries]
 +
 +
[https://github.com/EttusResearch/uhd UHD Source Code on Github]
 +
 +
==Choosing a Host Interface==
 +
 +
===10 Gigabit Ethernet===
 +
'''Recommended 10 Gigabit Ethernet Cards'''
 +
* Intel X520-DA2 - Previous generation PCIe Gen 2 adapter. Mature and stable 10GbE adapter, works out-of-the-box with Ubuntu 14.04 LTS and 16.04 LTS
 +
** [http://ark.intel.com/products/39776/Intel-Ethernet-Converged-Network-Adapter-X520-DA2 Intel® Ethernet Converged Network Adapter X520-DA2]
 +
* Intel X520-DA1 - Previous generation PCIe Gen 2 adapter  Mature and stable 10GbE adapter, works out-of-the-box with Ubuntu 14.04 LTS and 16.04 LTS
 +
** [http://ark.intel.com/products/68669/Intel-Ethernet-Converged-Network-Adapter-X520-DA1 Intel® Ethernet Converged Network Adapter X520-DA1 ]
 +
* Intel X710-DA2 - New PCIe Gen 3 adapter
 +
** [http://ark.intel.com/products/83964/Intel-Ethernet-Converged-Network-Adapter-X710-DA2 Intel® Ethernet Converged Network Adapter X710-DA2 ]
 +
* Intel X710-DA4 - New PCIe Gen 3 adapter
 +
** [http://ark.intel.com/products/83965/Intel-Ethernet-Converged-Network-Adapter-X710-DA4 Intel® Ethernet Converged Network Adapter X710-DA4 ]
 +
 +
'''Additional Links and Resources for Intel 10GbE adapters'''
 +
* [http://ark.intel.com/compare/39776,83964,83965 Compare Intel® Products]
 +
 +
==International Power Supply Options==
 +
The power supply provided with the USRP N310 kit is packaged with a power cord that is compatible with power outlets in the US/Japan.  If you are not using the USRP N310 in the US/Japan, we recommend purchasing the International USRP N310 Power Cord set. 
 +
 +
 +
==Guidance on SFP+ Adapters for Fiber Connectivity on USRP N310==
 +
 +
Ettus Research currently offers direct-connect, copper cabling accessories for the USRP N310. However, it is also possible to use multi-mode fiber instead of copper connections for these devices. In this section, we will provide general guidance on the types of fiber adapters and cables that can be used with these products.
 +
General Guidance on SFP+ Adapters
 +
 +
The USRP N310 USRP is compatible with most brands of SFP+ fiber adapters. In some cases, other equipment in the systems such as 1/10 Gigabith Ethernet switches are only compatible with specific brands of SFP+ adapters and cables. As a general rule, we recommend checking compatibility with the switches and network cards in your system before purchasing an adapter.
 +
 +
Ettus Research does test the USRP N310 USRP devices with our [https://www.ettus.com/product/details/10GIGE-KIT 10 Gigabit Ethernet Connectivity Kit] and a Blade Networks G8124 1/10 GigE switch. Here are is a list of known-good cables and adapters.
 +
 +
Ettus Research has only tested multi-mode fiber accessories.
 +
 +
===Known-Good Adapters===
 +
* [http://approvedoptics.com/blade-networks-bn-ckm-sp-sr/ Approved Optics BN-CKM-SP-SR-A]
 +
 +
===Known-Good Cables===
 +
* [http://www.colfaxdirect.com/store/pc/viewPrd.asp?idproduct=1696 Elpeus 10GbE SFP+ AOC Cable, 3 meters]
 +
 +
 +
[[Category:Hardware Resources]]

Revision as of 10:39, 1 March 2018

Device Overview

The USRP N310 is a networked software defined radio that provides reliability and fault-tolerance for deployment in large scale and distributed wireless systems. This device simplifies control and management of a network of radios by introducing the unique capability to remotely perform tasks such as debugging, updating software, rebooting, factory resetting, self-testing, and monitoring system health. The USRP N310 is an all-in-one device that includes two AD9371 transceivers, the Zynq-7100 SoC baseband processor, two SFP+ ports, a built-in GPSDO module, and various other peripheral and synchronization features.

Key Features

N310

  • Xilinx Xilinx Zynq-7100 FPGA SoC
  • Dual-core ARM A9 866 MHz CPU
  • 4 RX, 4TX in half-wide RU form factor
  • 10 MHz – 6 GHz extended frequency range
  • Up to 100 MHz of instantaneous bandwidth per channel
  • RX, TX filter bank
  • 16 bit ADC, 14 bit DAC
  • Configurable sample rates: 122.88, 125, and 153.6 MS/s
  • Two SFP+ ports (1 GbE, 10 GbE, Aurora)
  • RJ45 (1 GbE)
  • 10 MHz clock reference
  • PPS time reference
  • External RX, TX LO input ports
  • Built-in GPSDO
  • 1 Type A USB host port
  • 1 micro-USB port (serial console, JTAG)
  • Trusted Platform Module v1.2
  • Watchdog timer
  • OpenEmbedded Linux
  • High channel density
  • Reliable and fault-tolerant deployment
  • Remote management capability
  • Stand-alone operation
n310 kit.png

RF Specifications

Transmitter

  • Number of channels: 4
  • Frequency Range: 10 MHz to 6 GHz
  • Maximum instantaneous bandwidth: 100 MHz
  • Minimum frequency step
    • 7.32 Hz @ 122.88 MHz sample rate
    • 7.45 Hz @ 125 MHz sample rate
    • 9.15 Hz @ 153.6 MHz sample rate
  • Maximum output power (P​ out​ ): See Table 1
  • Gain range
    • -30 dB to 25 dB (10 MHz to 300 MHz)
    • -30 dB to 20 dB (300 MHz to 6 GHz)
  • Gain step: 1 dB
  • Supported I/Q sample rates:
    • 122.88 MHz, 125 MHz, 153.6 MHz
  • Spurious-free dynamic range (SFDR) > 50 dBc
  • Output third-order intercept (OIP3) See Table 2


Frequency Maximum Output Power
10 MHz to 500 MHz +16 dBm
> 500 MHz to 1 GHz +18 dBm
> 1 GHz to 4 GHz +18 dBm
> 4 GHz to 6 GHz +12 dBm

Table 1: Maximum Output Power

Frequency Output Third-Order Intercept (IP3)
10 MHz to 2 GHz > 30 dBm
> 2 GHz to 4 GHz > 20 dBm
> 4 GHz to 6 GHz > 10 dBm

Table 2: Third-Order Intercept (IP3)


Receiver

  • Number of channels: 4
  • Frequency Range: 10 MHz to 6 GHz
  • Maximum instantaneous bandwidth: 100 MHz
  • Minimum frequency step
    • 7.32 Hz @ 122.88 MHz sample rate
    • 7.45 Hz @ 125 MHz sample rate
    • 9.15 Hz @ 153.6 MHz sample rate
  • Gain step: 1
  • Maximum recommended input power (P​ in​ ) 1 dB: -15 dBm
  • Noise figure: > 50 dBc
  • Spurious-free dynamic range (SFDR) See Table 3
  • Third-order intermodulation distortion (IMD3) See Table 4
  • Supported I/Q sample rates
    • 122.88 MHz, 125 MHz, 153.6 MHz


Frequency RX2 Noise Figure TX/RX Noise Figure
1.8 GHz 5.8 dB 6.8 dB
2.4 GHz to 2.6 GHz 6.5 dB 7.5 dB
3.3 GHz to 4.8 GHz 5.5 dB 6.0 dB
5.0 GHz to 5.8 GHz 7.0 dB 7.5 dB

Table 3: Noise Figure


Frequency RX IMD3
0.5 GHz to 3 GHz < -80 dBc
> 3 GHz to 4 GHz < -74 dBc
> 4 GHz to 6 GHz < -81 dBc

Table 4: RX Third-Order Intermodulation Distortion (IMD3)

  • Noise figure is measured at maximum gain state on receiver signal path.


Onboard DRAM

  • DDR3 Memory size
    • 2,048 MB (PL)
    • 1,024 MB (PS)


Power

You must use either the Level VI Efficiency power supply provided in the shipping kit, or another UL listed ITE power supply marked ​LPS, with the USRP N310.

  • Input voltage: 12 VDC
  • Input current: 7.0 A, maximum
  • Typical power consumption: 50 W to 80 W, varies by application

Hardware Specifications

  • Ettus Research recommends to always use the latest stable version of UHD
  • If you need to clean the module, wipe it with a dry towel.

N310

  • Current Hardware Revision: A
  • Minimum version of UHD required: 3.11.0.0

Physical Specifications

Dimensions

(L × W × H)

  • 35.71 cm × 21.11 cm × 4.37 cm
  • 14.06 in. × 8.31 in. × 1.72 in.

Weight

  • 3.13 kg

Environmental Specifications

Operating Temperature Range

  • N310: 0 to 50 °C

Storage Temperature Range

  • N310: -40 to 70 °C

Operating Humidity Range

  • 10% to 90% non-condensing

Schematics

N310

N310 Schematics

GPSDO

  • Support GPSDO NMEA Strings

Sensors

You can query the lock status with the gps_locked sensor, as well as obtain raw NMEA sentences using the gps_gprmc, and gps_gpgga sensors. Location information can be parsed out of the gps_gpgga sensor by using gpsd or another NMEA parser.

FPGA

FPGA User Modifications

The Verilog code for the FPGA in the USRP N300/N310 is open-source, and users are free to modify and customize it for their needs. However, certain modifications may result in either bricking the device, or even in physical damage to the unit. Specifically, changing the I/O interface of the FPGA in any way, or modifying the pin and timing constraint files, could result in physical damage to other components on the motherboard, external to the FPGA, and doing this will void the warranty. Also, even if the PCIe interface is not being used, you cannot remove or reassign these pins in the constraint file. The constraint files should not be modified. Please note that modifications to the FPGA are made at the risk of the user, and may not be covered by the warranty of the device.

Interfaces and Connectivity

Follow the links below for additional information on configuring each interface for the USRP N300 or N310 SDRs.

  • 100 MS/s Full Duplex @ 16-bit

Front Panel

  • PWR: Power switch
  • RF 0 Group
    • TX/RX SMA/LED: RF Input Port / Indicates that data is streaming on the TX/RX channel on daughterboard 0, channel 0
    • RX2 SMA/LED: RF Input Port / Indicates that data is streaming on the RX2 channel on daughterboard 0, channel 0
  • RF 1 Group
    • TX/RX SMA/LED: RF Input Port / Indicates that data is streaming on the TX/RX channel on daughterboard 0, channel 1
    • RX2 SMA/LED: RF Input Port / Indicates that data is streaming on the RX2 channel on daughterboard 0, channel 1
  • RF 2 Group
    • TX/RX SMA/LED: RF Input Port / Indicates that data is streaming on the TX/RX channel on daughterboard 1, channel 0
    • RX2 SMA/LED: RF Input Port / Indicates that data is streaming on the RX2 channel on daughterboard 1, channel 0
  • RF 3 Group
    • TX/RX SMA/LED: RF Input Port / Indicates that data is streaming on the TX/RX channel on daughterboard 1, channel 1
    • RX2 SMA/LED: RF Input Port / Indicates that data is streaming on the RX2 channel on daughterboard 1, channel 1
  • LO IN 0/1
    • TX: Input port for TX LO of Daughterboard 0
    • RX: Input port for RX LO of Daughterboard 0
  • LO IN 2/3
    • TX: Input port for TX LO of Daughterboard 1
    • RX: Input port for RX LO of Daughterboard 1
  • GPIO
    • GPIO: DB15 GPIO Interface. Additional details below.


 n310 front.png

Rear Panel

  • GPS ANT: Connection for the GPS antenna
  • REF IN: Reference clock input
  • PPS/TRIG IN: Input port for the PPS signal
  • TRIG OUT: Output port for the exported reference clock
  • PWR: Connector for the USRP N310 Series power supply
  • RESET: Input button to reset device
  • MicroSD: MicroSD Card for OE Linux File System
  • JTAG: Micro USB connector for the on-board USB-JTAG programmer
  • USB 2.0: Host USB connector to ARM CPU
  • SFP+: 1/10Gb SFP+ ports for Ethernet interfaces
  • 10/1000/1000: 10/100/1000 Mb Ethernet interface to ARM CPU
 n310 back.png

Ref Clock - 10 MHz

Using an external 10 MHz reference clock, a square wave will offer the best phase noise performance, but a sinusoid is acceptable. The power level of the reference clock cannot exceed +10 dBm.

PPS - Pulse Per Second

Using a PPS signal for timestamp synchronization requires a square wave signal with the following a 5Vpp amplitude.

To test the PPS input, you can use the following tool from the UHD examples:

  • <args> are device address arguments (optional if only one USRP device is on your machine)
   cd <install-path>/lib/uhd/examples ./test_pps_input –args=<args>


Front Panel GPIO

The GPIO port is not meant to drive big loads. You should not try to source more than 5mA per pin.

The +3.3V is for ESD clamping purposes only and not designed to deliver high currents.


Power on state

The hardware power on state and UHD initial state for the front-panel GPIOs is high-Z. For the N310, there are no external pull-ups/pull-downs for the GPIO pins, but the FPGAs do have them and they are configured as follows: N310: pull-down.

Pin Mapping

  • Pin 1: +3.3V
  • Pin 2: Data[0]
  • Pin 3: Data[1]
  • Pin 4: Data[2]
  • Pin 5: Data[3]
  • Pin 6: Data[4]
  • Pin 7: Data[5]
  • Pin 8: Data[6]
  • Pin 9: Data[7]
  • Pin 10: Data[8]
  • Pin 11: Data[9]
  • Pin 12: Data[10]
  • Pin 13: Data[11]
  • Pin 14: 0V
  • Pin 15: 0V

Note: Please see the E3x0/X3x0/N3x0 GPIO API for information on configuring and using the GPIO bus.

Certifications

RoHS

As of December 1st, 2010 all Ettus Research products are RoHS compliant unless otherwise noted. More information can be found at http://ettus.com/legal/rohs-information

China RoHS

Management Methods for Controlling Pollution Caused by Electronic Information Products Regulation

Chinese Customers

National Instruments is in compliance with the Chinese policy on the Restriction of Hazardous Substances (RoHS) used in Electronic Information Products. For more information about the National Instruments China RoHS compliance, visit ni.com/environment/rohs_china.

Downloads

FPGA Resources

UHD Stable Binaries

UHD Source Code on Github

Choosing a Host Interface

10 Gigabit Ethernet

Recommended 10 Gigabit Ethernet Cards

Additional Links and Resources for Intel 10GbE adapters

International Power Supply Options

The power supply provided with the USRP N310 kit is packaged with a power cord that is compatible with power outlets in the US/Japan. If you are not using the USRP N310 in the US/Japan, we recommend purchasing the International USRP N310 Power Cord set.


Guidance on SFP+ Adapters for Fiber Connectivity on USRP N310

Ettus Research currently offers direct-connect, copper cabling accessories for the USRP N310. However, it is also possible to use multi-mode fiber instead of copper connections for these devices. In this section, we will provide general guidance on the types of fiber adapters and cables that can be used with these products. General Guidance on SFP+ Adapters

The USRP N310 USRP is compatible with most brands of SFP+ fiber adapters. In some cases, other equipment in the systems such as 1/10 Gigabith Ethernet switches are only compatible with specific brands of SFP+ adapters and cables. As a general rule, we recommend checking compatibility with the switches and network cards in your system before purchasing an adapter.

Ettus Research does test the USRP N310 USRP devices with our 10 Gigabit Ethernet Connectivity Kit and a Blade Networks G8124 1/10 GigE switch. Here are is a list of known-good cables and adapters.

Ettus Research has only tested multi-mode fiber accessories.

Known-Good Adapters

Known-Good Cables

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