Difference between revisions of "Debugging FPGA images"
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| − | When you are developing your own application, you might come to the point on which you | + | When you are developing your own application, you might come to the point on which you would like to build an FPGA image for your USRP. You might want to modify part of the cores, add some custom functionality, or even add your custom RFNoC block! For that you might follow tutorials such as the [[Getting_Started_with_RFNoC_Development#Building the FPGA image|Building the FPGA image]] section of one our "getting started" guides. |
But how about debugging your HDL code? This comes really handy when you want to follow closely the behaviour of your signals within your hardware design. This Application Note will follow the basic steps needed to create a "chipscope image", which allow you to use the Vivado GUI visual tools to debug your design. | But how about debugging your HDL code? This comes really handy when you want to follow closely the behaviour of your signals within your hardware design. This Application Note will follow the basic steps needed to create a "chipscope image", which allow you to use the Vivado GUI visual tools to debug your design. | ||
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| + | Before we start, this App note assumes that you have been working already with some fpga code and you want to debug it. Being this the case, we assume that you have UHD installed, the FPGA repository cloned, the right version of Xilinx Vivado installed (by the moment this is being written we use Vivado 2015.4) and its environment initialized. If not, we assume you are familiar on how to do the previously noted procedures. | ||
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| + | For illustration purposes, here we are going to check the status of some of the output signals of one of the RFNoC blocks we currently provide. However, the sane procedure can be used to check the status of any signal within your hardware code, being input, output, or intermediate signal, and being the code a core description, a module for your library or your custom RFNoC block. | ||
Revision as of 11:34, 6 October 2016
When you are developing your own application, you might come to the point on which you would like to build an FPGA image for your USRP. You might want to modify part of the cores, add some custom functionality, or even add your custom RFNoC block! For that you might follow tutorials such as the Building the FPGA image section of one our "getting started" guides.
But how about debugging your HDL code? This comes really handy when you want to follow closely the behaviour of your signals within your hardware design. This Application Note will follow the basic steps needed to create a "chipscope image", which allow you to use the Vivado GUI visual tools to debug your design.
Before we start, this App note assumes that you have been working already with some fpga code and you want to debug it. Being this the case, we assume that you have UHD installed, the FPGA repository cloned, the right version of Xilinx Vivado installed (by the moment this is being written we use Vivado 2015.4) and its environment initialized. If not, we assume you are familiar on how to do the previously noted procedures.
For illustration purposes, here we are going to check the status of some of the output signals of one of the RFNoC blocks we currently provide. However, the sane procedure can be used to check the status of any signal within your hardware code, being input, output, or intermediate signal, and being the code a core description, a module for your library or your custom RFNoC block.
