Difference between revisions of "RFNoC (UHD 3.0)"

Revision as of 13:31, 8 December 2016

Overview

Current FPGAs, like the Xilinx Kintex-7 and Zynq-7000 series used in third generation USRP SDRs, have incredible computational capability, but taking advantage of that capability can be difficult when using traditional FPGA design flows. RFNoC is designed to allow you to efficiently harness the full power of the latest generations of FPGAs without being an expert firmware developer. It provides the capability to create FPGA applications as easily as you can create GNU Radio flowgraphs. This includes the ability to seamlessly transfer data to & from an FPGA, from the host PC in your application, dramatically improving the ease of FPGA off-loading. Having a system-level view of the entire SDR application running on both the FPGA and the host PC enables far superior development and debugging. Mixing and matching host-based and FPGA-based processing is transparent to you, and that processing can scale across multiple FPGAs and devices across a network.

Supported Devices

• E310/E312
• X300/X310

Sample of Available Blocks

• FIFO
• FFT
• FIR
• fosphor (real-time spectrum analyzer)
• Decimator (Keep 1 in N)
• Log Power Calculator
• Radio Interface
• Vector IIR (moving average)
• Window multiplier (for FFT)
• OFDM: Burst detection + synchronization, equalizer, packet demodulator
• and more...

RFNoC Resources

2016

• Getting Started with RFNoC Development with PyBOMBS
• Getting Started with RFNoC Development
• GNU Radio 2016 Conference Presentation

2015

• Virginia Tech Video Presentation
• Virginia Tech Presentation - Introduction to RFNoC
• Virginia Tech Presentation - RFNoC Deep Dive: Host Side
• Virginia Tech Presentation - RFNoC Deep Dive: FPGA

2013

• sigcom 2013 Paper