RFNoC Frequently Asked Questions

Configuring the Stream Endpoint Buffer Size in RFNoC

What is the SEP buffer size?

Each stream endpoint (SEP) has an ingress buffer to store data received from others stream endpoints. This size of this buffer affects the data transfer rate that can be achieved when streaming to that endpoint. A larger ingress buffer in the stream endpoint means that there is more space to put data, minimizing idle time on the network. Additionally, streamers can queue up data before it is needed, reducing the chance of a buffer underflow.

How do I set the SEP buffer size?

The stream endpoint buffer size is set by adding a parameter under the endpoint you want to configure in the RFNoC image core YAML file. There are two parameters you can use to set the stream endpoint ingress buffer size in your RFNoC image core YAML file.

• buff_size: Buffer size in CHDR words. The size in bytes depends on the CHDR width. For example, if the chdr_width parameter for the device is 64, then each CHDR word is 8 bytes. So a buff size of 32768 would be 262,144 bytes or 256 KiB. See here for an example.
• buff_size_bytes: Buffer size in bytes. See here for an example.

To what value should I set the SEP buffer size?

The buffer size should be a power of two in size to make optimal use of FPGA RAM resources. The default FPGA bitstreams typically set them to the largest size the FPGA can fit in order to maximize performance. Here are some general recommendations:

• Set to 0 if you don't need to send data to that SEP.
• Set to 8192 bytes (8 KiB = 1 MTU) minimum in order to stream data packets.
• Set to 32768 bytes (32 KiB = 4 MTU) in order to stream at maximum rates between SEPs on the same FPGA.
• Set to 262144 bytes (256 KiB = 32 MTU) or lager for high performance streaming between a host computer and the FPGA.

Note that the requirements are application-dependent, so optimal sizes for your application may be different. MTU refers to the maximum transmission unit, which is the largest CHDR packet supported by the FPGA.

If you need to free up FPGA resources (particularly block RAM) for your application, you can reduce the SEP buffer sizes. Just keep in mind that the maximum streaming rate may be affected.

RFNoC Clocks

What clocks are available for me to use?

Each device has different clocks available. See below for a list of clocks exposed to RFNoC. Although they have intended purposes, you can use any of these clocks for any purpose. The rfnoc_chdr_clock is a good default choice. This clock is always available in your block, even if it is not explicitly connected in the RFNoC image YAML description.

What are the clock frequencies?

See the table below for the clock rates. The radio clock rate depends on the master clock rate.

E31x

Clock Name	Description	Frequency
rfnoc_chdr	RFNoC CHDR clock	100 MHz
dram	DRAM interface clock	100 MHz
radio	Radio interface clock	Same as master clock rate

E320

Clock Name	Description	Frequency
rfnoc_chdr	RFNoC CHDR clock	200 MHz
dram	DRAM interface clock	166.667 MHz
radio	Radio interface clock	Same as master clock rate (200 kHz to 61.44 MHz)

N300/N310

Clock Name	Description	Frequency
rfnoc_chdr	RFNoC CHDR clock	200 MHz
dram	DRAM interface clock	303.189 MHz
radio	Radio interface clock	Same as master clock rate (122.88 MHz, 125.0 MHz, or 153.6 MHz)

N32x

Clock Name	Description	Frequency
rfnoc_chdr	RFNoC CHDR clock	187.5 MHz
dram	DRAM interface clock	303.819 MHz
radio	Radio interface clock	Same as master clock rate (200 MHz, 245.76 MHz, or 250 MHz)

X310

Clock Name	Description	Frequency
rfnoc_chdr	RFNoC CHDR clock	187.5 MHz
ce	Compute Engine clock	214.286 MHz
dram	DRAM interface clock	300 MHz
radio	Radio interface clock	Same as master clock rate (184.32 MHz or 200 MHz)

X410

Clock Name	Description	Frequency
rfnoc_chdr	RFNoC CHDR clock	200 MHz
dram	DRAM interface clock	250 MHz
radio	Radio interface clock	122.88 MHz when master clock rate is 122.88, 245.76, or 491.52 MHz 125 MHz when master clock rate is 125, 250, or 500 MHz
radio_2x	Radio interface clock 2x	Twice the frequency of radio_clk

How do I add a clock with a different frequency?

Adding custom clocks is not directly supported yet. Describing them in the YAML file will not cause them to be generated for you. If you can't use any of the available clocks, you can modify the HDL code to generate a clock.

If you only need the clock within your own RFNoC block, you can modify the HDL for your block to generate the clock that you need from one of the available clocks. To do this, add a new clock to your block's YAML description, connect the available clock to your block in the YAML description of your RFNoC image, then add a Xilinx MMCM IP instance to your block's HDL and connect the available clock to its input.

If the clock is needed by multiple RFNoC blocks, or if you want to change an existing clock, you can modify the HDL for the USRP you are using to add or change a clock. If you add a new clock to the RFNoC image core, you must also update the BSP YAML file (located in <repo>/host/include/uhd/rfnoc/core) so that the rfnoc_image_builder knows that the clock exists. How and where the clocks are generated varies between USRPs. Please refer to the source code for that USRP (<repo>/fpga/usrp3/top).