X300/X310 Device Recovery

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Application Note Number

AN-305

Revision History

Date Author Details
2017-05-02 Nate Temple Initial creation

Abstract

This application note covers the details of recovering the USRP X300/X310 via JTAG.

Overview

This application note covers the process of recovering the USRP X300/X310 by flashing the FPGA image via the JTAG interface.

Note: Linux only.

Manual

For reference, the user manual page for the X300/X310 is at the link below.

http://files.ettus.com/manual/page_usrp_x3x0.html

Required Tools

  • Computer with USB2/3 and 1 GbE or 10GbE Interface
  • Ubuntu 14.x or 16.x Installation
  • UHD Installation
  • USB2 Cable
  • SFP+ / RJ45 Adapter
  • Ethernet Cable

Prerequisites

This application note assumes you have a Ubuntu 14.x or 16.x Linux installation. You should also have a working UHD installation. If you do not have UHD installed, please reference the Building and Installing the USRP Open-Source Toolchain (UHD and GNU Radio) on Linux Application Note.

You will need to have the matching FPGA images downloaded before proceeding for your UHD installation. If you do not have the FPGA images downloaded, run the command:

   sudo uhd_images_downloader

Verify you have the FPGA images downloaded by running the command:

   ls -alh /usr/local/share/uhd/images/usrp_x3*
x300 recovery 19.png

Installing Xilinx Vivado Lab 2015.4

You will need to download and install Xilinx Vivado Lab Edition 2015.4 in order to flash the USRP X300/X310 via JTAG. Xilinx Vivado Lab Edition 2015.4 can be downloaded at the following link:

Note: Xilinx Vivado 2015.4 must be used. If you already have Xilinx Vivado Design or System Edition (2015.4) installed, they will work in place of the Lab Edition. If Design or System Edition is used, the paths may differ from described within this application note, however the process is the same.

https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive.html

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After the download is complete, verify the MD5 sum of the file:

   cd ~/Downloads
   md5sum Xilinx_Vivado_Lab_Lin_2015.4_1118_2.tar.gz

Note: The filename and MD5 hash may differ from the screen capture shown. Verify the MD5 sum against the hash listed on the Xilinx download page.

x300 recovery 2.png

Next, decompress the downloaded tarball:

   tar -zxvf Xilinx_Vivado_Lab_Lin_2015.4_1118_2.tar.gz

Next, go into the new directory and run the xsetup installer (It requires sudo permissions to install):

   cd Xilinx_Vivado_Lab_Lin_2015.4_1118_2
   sudo ./xsetup
x300 recovery 3.png


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This will launch the Xilinx Vivado Lab installer.

x300 recovery 5.png


You will be prompted that a newer version is available, ignore this popup and click Continue to install Xilinx Vivado Lab 2015.4.

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The installer will then be at a Welcome screen, click Next.

x300 recovery 8.png


You will then be prompted to accept the various License Agreements, click Next.

x300 recovery 9.png


You will then be prompted to select the install options. It is suggested to leave the default values, click Next.

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You will then be prompted with the installation locations. It is suggested to leave the default values, click Next.

x300 recovery 11.png


You will then be prompted to create the directory /opt/Xilinx. Click Yes.

x300 recovery 12.png


Finally, you will be at the Installation Summary prompt. Click Install.

x300 recovery 13.png


The installation process should only take a minute or two.

x300 recovery 14.png


You will then be prompted that the installation was successful. Click Ok, and the installer will close.

x300 recovery 15.png

Installing the Digilent Cable Driver

In order to use the JTAG interface built into the USRP X300/X310 front panel, you will need to install the Digilent Cable Driver. It is included with the Xilinx Vivado Lab Edition package.

Navigate to the folder /opt/Xilinx/Vivado_Lab/2015.4/data/xicom/cable_drivers/lin64/install_script/install_drivers, and run the installer script.

   cd /opt/Xilinx/Vivado_Lab/2015.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
   sudo ./install_digilent.sh
x300 recovery 16.png


Next, reload the UDEV rules

   sudo udevadm control --reload

Configuring Network Interface

You will need to set your ethernet interface that will be connected to the USRP X300/X310 to a static IP address of 192.168.10.1 along with setting a MTU of 1500.

x300 recovery 36.png
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Connect the X300/X310

Connect the USRP X300/X310 with the USB2 cable via the JTAG port on the front face plate. You can also attach the SFP+/RJ45 adapter to Port 0 and connect your computer via ethernet.

Power on the USRP X300/X310.

Starting Xilinx Vivado Lab Edition

Start by navigating back to your home directory:

   cd ~/

Next, start Xilinx Vivado Lab

   /opt/Xilinx/Vivado_Lab/2015.4/bin/vivado_lab
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Open the Hardware Manager

x300 recovery 21.png


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Next, within the menu the of the Hardware Manager select Tools -> Auto Connect.

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The details of the FPGA should populate the window on the left side of the Hardware Manager.

x300 recovery 24.png


Right click on the FPGA listed, and select Program Device.

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This will popup a new window. Click on the file selection button and navigate to the location of the UHD FPGA images, and select the correct FPGA image for your device. (/usr/local/share/uhd/images)

Note: Select the correct FPGA image that matches your USRP (either _x300 or _x310) with the .bit file extension. It is recommended to select the _HG FPGA image, which will initialize Port 0 as 1 GbE and Port 1 as 10 GbE. Advanced users operating with dual 10 GbE may select the _XG image, however you will need to adjust the instructions listed within this document to match the dual 10GbE configuration (IP Addresses, MTU settings, etc).

x300 recovery 26.png
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Next, click Program.

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A progress bar will popup as the FPGA is programmed.

x300 recovery 31.png


Once the programming is completed, close Vivado Lab.

x300 recovery 32.png


Return to a terminal and attempt to ping the USRP X300/X310.

   ping 192.168.10.2
x300 recovery 34.png

Stop the ping with CTRL-C.

At this point, if you're able to ping the USRP X300/X310, attempt to run the UHD utility uhd_usrp_probe.

   uhd_usrp_probe

Example output from uhd_usrp_probe:

user@host:~$ uhd_usrp_probe 
linux; GNU C++ version 5.4.0 20160609; Boost_105800; UHD_003.010.001.HEAD-0-gc705922a

-- X300 initialization sequence...
-- Determining maximum frame size... 1472 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...
-- Setup RF frontend clocking...
-- Radio 1x clock:200
-- [DMA FIFO] Running BIST for FIFO 0... pass (Throughput: 1304.3MB/s)
-- [DMA FIFO] Running BIST for FIFO 1... pass (Throughput: 1300.5MB/s)
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- Performing timer loopback test... pass
-- Performing timer loopback test... pass
  _____________________________________________________
 /
|       Device: X-Series Device
|     _____________________________________________________
|    /
|   |       Mboard: X310
|   |   revision: 8
|   |   revision_compat: 7
|   |   product: 30818
|   |   mac-addr0: 00:00:00:00:00:00
|   |   mac-addr1: 00:00:00:00:00:00
|   |   gateway: 192.168.10.1
|   |   ip-addr0: 192.168.10.2
|   |   subnet0: 255.255.255.0
|   |   ip-addr1: 192.168.20.2
|   |   subnet1: 255.255.255.0
|   |   ip-addr2: 192.168.30.2
|   |   subnet2: 255.255.255.0
|   |   ip-addr3: 192.168.40.2
|   |   subnet3: 255.255.255.0
|   |   serial: xxxxxxxx
|   |   FW Version: 5.1
|   |   FPGA Version: 33.0
|   |   RFNoC capable: Yes
|   |   
|   |   Time sources:  internal, external, gpsdo
|   |   Clock sources: internal, external, gpsdo
|   |   Sensors: ref_locked
|   |     _____________________________________________________
|   |    /
|   |   |       RX Dboard: A
|   |   |   ID: UBX-160 v1 (0x007a)
|   |   |   Serial: xxxxxxxx
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       RX Frontend: 0
|   |   |   |   Name: UBX RX
|   |   |   |   Antennas: TX/RX, RX2, CAL
|   |   |   |   Sensors: lo_locked
|   |   |   |   Freq range: 10.000 to 6000.000 MHz
|   |   |   |   Gain range PGA0: 0.0 to 31.5 step 0.5 dB
|   |   |   |   Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
|   |   |   |   Connection Type: IQ
|   |   |   |   Uses LO offset: No
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       RX Codec: A
|   |   |   |   Name: ads62p48
|   |   |   |   Gain range digital: 0.0 to 6.0 step 0.5 dB
|   |     _____________________________________________________
|   |    /
|   |   |       RX Dboard: B
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       RX Frontend: 0
|   |   |   |   Name: Unknown (0xffff) - 0
|   |   |   |   Antennas: 
|   |   |   |   Sensors: 
|   |   |   |   Freq range: 0.000 to 0.000 MHz
|   |   |   |   Gain Elements: None
|   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz
|   |   |   |   Connection Type: IQ
|   |   |   |   Uses LO offset: No
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       RX Codec: B
|   |   |   |   Name: ads62p48
|   |   |   |   Gain range digital: 0.0 to 6.0 step 0.5 dB
|   |     _____________________________________________________
|   |    /
|   |   |       TX Dboard: A
|   |   |   ID: UBX-160 v1 (0x0079)
|   |   |   Serial: xxxxxxxx
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       TX Frontend: 0
|   |   |   |   Name: UBX TX
|   |   |   |   Antennas: TX/RX, CAL
|   |   |   |   Sensors: lo_locked
|   |   |   |   Freq range: 10.000 to 6000.000 MHz
|   |   |   |   Gain range PGA0: 0.0 to 31.5 step 0.5 dB
|   |   |   |   Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
|   |   |   |   Connection Type: QI
|   |   |   |   Uses LO offset: No
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       TX Codec: A
|   |   |   |   Name: ad9146
|   |   |   |   Gain Elements: None
|   |     _____________________________________________________
|   |    /
|   |   |       TX Dboard: B
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       TX Frontend: 0
|   |   |   |   Name: Unknown (0xffff) - 0
|   |   |   |   Antennas: 
|   |   |   |   Sensors: 
|   |   |   |   Freq range: 0.000 to 0.000 MHz
|   |   |   |   Gain Elements: None
|   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz
|   |   |   |   Connection Type: IQ
|   |   |   |   Uses LO offset: No
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       TX Codec: B
|   |   |   |   Name: ad9146
|   |   |   |   Gain Elements: None
|   |     _____________________________________________________
|   |    /
|   |   |       RFNoC blocks on this device:
|   |   |   
|   |   |   * DmaFIFO_0
|   |   |   * Radio_0
|   |   |   * Radio_1
|   |   |   * DDC_0
|   |   |   * DDC_1
|   |   |   * DUC_0
|   |   |   * DUC_1


If running uhd_usrp_probe is successful, proceed with flashing the FPGA image with the UHD utility uhd_image_loader.

Note: Flashing the FPGA image via JTAG only does not write the FPGA image to EEPROM, you must run the uhd_image_loader to write the FPGA image to the internal EEPROM.

   uhd_image_loader --args "type=x300,addr=192.168.10.2,type=HG"
x300 recovery 37.png


When uhd_image_loader has completed the flashing process, it will recommend to power cycle the USRP X300/X310.

x300 recovery 38.png


Power off the USRP X300/X310, remove the JTAG USB cable, and then power on the USRP X300/X310.


The USRP X300/X310 is now recovered. You should be able to ping, run uhd_usrp_probe and any other UHD utility/application as normal.