Difference between revisions of "E310/E312"

Revision as of 14:57, 14 May 2016 (view source) Ettus (Talk | contribs) (→‎Key Component Datasheets) ← Older edit		Revision as of 14:58, 14 May 2016 (view source) Ettus (Talk | contribs) (→‎Key Component Datasheets) Newer edit →
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	|[http://datasheets.maximintegrated.com/en/ds/DS1339-DS1339U.pdf DS1339,SM]		|[http://datasheets.maximintegrated.com/en/ds/DS1339-DS1339U.pdf DS1339,SM]
−	|	+	|Real-Time Clock
	|U6 (9)		|U6 (9)
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Revision as of 14:58, 14 May 2016

Device Overview

The USRP E310 offers a portable stand-alone SDR platform designed for field deployment. The flexible 2x2 MIMO AD9361 transceiver from Analog Devices provides up to 56 MHz of instantaneous bandwidth and spans frequencies from 70 MHz – 6 GHz to cover multiple bands of interest.

Key Features

E310

Xilinx Zynq 7020 SoC: 7 Series FPGA with ARM Cortex A9 667 MHz dual-core processor Analog Devices AD9361 RFIC direct-conversion transceiver Frequency range: 70 MHz - 6 GHz Up to 56 MHz of instantaneous bandwidth 2x2 MIMO transceiver Up to 10 MS/s sample data transfer rate to ARM processor RX, TX filter banks Integrated GPS receiver 9-axis inertial measurement unit RF Network on Chip (RFNoC™) FPGA development framework support

E312

Battery Operated Xilinx Zynq 7020 SoC: 7 Series FPGA with ARM Cortex A9 866 MHz dual-core processor Analog Devices AD9361 RFIC direct-conversion transceiver Frequency range: 70 MHz - 6 GHz Up to 56 MHz of instantaneous bandwidth 2x2 MIMO transceiver Up to 10 MS/s sample data transfer rate to ARM processor RX, TX filter banks Integrated GPS receiver 9-axis inertial measurement unit RF Network on Chip (RFNoC™) FPGA development framework support

RF Specifications

RF Performance

• SSB/LO Suppression -35/50 dBc
• Phase Noise 3.5 GHz 1.0 deg RMS
• Phase Noise 6 GHz 1.5 deg RMS
• Power Output >10dBm
• IIP3 (@ typ NF) -20dBm
• Typical Noise Figure <8dB

Hardware Specifications

E310

• Details

E312

• Details

Clocks and Samples Rates

• FIXME NEEL

Physical Specifications

Dimensions

• 133 x 68 x 26.4 mm

Environmental Specifications

Operating Temperature Range

• E310 0-40 °C

Schematics

E310

E310 Schematics

E310 DB

E310 Architecture

Key Component Datasheets

Part Number	Description	Schematic ID (Page)
TXS02612RTWR	SDIO PORT EXPANDER	U23 (2)
XC7Z020-1CLG484CES9919	FPGA	U11 (2,3,4,8,11,13)
USB3340-EZK-TR	ULPI Transceiver	U33 (5)
AK4571VQP	Audio CODEC	U30 (6)
FT230XQ-R	UART Interface	U32 (6)
88E1512	Gigabit Ethernet Transceiver	U13 (7)
24LC024/SN	EEPROM	U5 (9)
DS1339,SM	Real-Time Clock	U6 (9)
ADT7408	Temperature Sensor	U8 (9)
MPU-9150	Motion Processing Unit	U3 (9)
BMP180	Digital pressure sensor	U4 (9)
BQ24192	Adapter Charger	U1 (10)
TPS54478	Step-Down Switcher	U20 (10)
MAX6510HAUT-T	Temperature Switches	U35 (10)
ATTINY88-MU	Microcontroller	U18 (10)
TPS61253YFF	Step-Up Converter	U19 (10)
AD9361 Product Page	2 x 2 RF Agile Transceiver	-
Xilinx Zynq Product Page	FPGA	-
InvenSense MPU-9150 Product Page	Motion Processing Unit	U3 (9)

Request a detailed whitepaper covering features and components from info@ettus.com

Mechanical Info

Weight

• Partial Enclosure 225 g
• Full Enclosure 375 g

Drawings

• E310 Drawings - File:E310 Dimensional Sketches.pdf

FPGA

• Utilization statistics are subject to change between UHD releases, current as of UHD 3.9.4

E310/E312

1. Slice Logic
--------------

+----------------------------+-------+-----------+-------+
|          Site Type         |  Used | Available | Util% |
+----------------------------+-------+-----------+-------+
| Slice LUTs                 | 36203 |     53200 | 68.05 |
|   LUT as Logic             | 28108 |     53200 | 52.83 |
|   LUT as Memory            |  8095 |     17400 | 46.52 |
|     LUT as Distributed RAM |   870 |           |       |
|     LUT as Shift Register  |  7225 |           |       |
| Slice Registers            | 36562 |    106400 | 34.36 |
|   Register as Flip Flop    | 36562 |    106400 | 34.36 |
|   Register as Latch        |     0 |    106400 |  0.00 |
| F7 Muxes                   |   376 |     26600 |  1.41 |
| F8 Muxes                   |   125 |     13300 |  0.93 |
+----------------------------+-------+-----------+-------+

3. Memory
---------

+-------------------+------+-----------+-------+
|     Site Type     | Used | Available | Util% |
+-------------------+------+-----------+-------+
| Block RAM Tile    |   97 |       140 | 69.28 |
|   RAMB36/FIFO*    |   90 |       140 | 64.28 |
|     RAMB36E1 only |   90 |           |       |
|   RAMB18          |   14 |       280 |  5.00 |
|     RAMB18E1 only |   14 |           |       |
+-------------------+------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1


4. DSP
------

+----------------+------+-----------+-------+
|    Site Type   | Used | Available | Util% |
+----------------+------+-----------+-------+
| DSPs           |  120 |       220 | 54.54 |
|   DSP48E1 only |  120 |           |       |
+----------------+------+-----------+-------+

Interfaces and Connectivity

• 10/100/1000 BASE-T Ethernet
• Stereo audio out, mono mic in
• Integrated GPS receiver
• Host USB support
• 9-axis IMU

Multiple Device Configuration

• [ADD]

Certifications

RoHS

As of December 1st, 2010 all Ettus Research products are RoHS compliant unless otherwise noted. More information can be found at http://ettus.com/legal/rohs-information

Certificate of Volatility

E310

• Media:volatility USRP E310 r1.pdf

E312

• Media:USRP E31x CoV.pdf

Downloads

FPGA Images

FPGA Images Read Me

FPGA Resources

UHD Stable Binaries

UHD Source Code on Github