Difference between revisions of "E310/E312"

Latest revision as of 17:36, 18 September 2023

Device Overview

The USRP E310 offers a portable stand-alone SDR platform designed for field deployment. The flexible 2x2 MIMO AD9361 transceiver from Analog Devices provides up to 56 MHz of instantaneous bandwidth and spans frequencies from 70 MHz – 6 GHz to cover multiple bands of interest.

Key Features

E310

Xilinx Zynq 7020 SoC: 7 Series FPGA with ARM Cortex A9 667 MHz dual-core processor Analog Devices AD9361 RFIC direct-conversion transceiver Frequency range: 70 MHz - 6 GHz Up to 56 MHz of instantaneous bandwidth 2x2 MIMO transceiver Up to 10 MS/s sample data transfer rate to ARM processor RX, TX filter banks Integrated GPS receiver 9-axis inertial measurement unit RF Network on Chip (RFNoC™) FPGA development framework support

E312

Battery Operated Xilinx Zynq 7020 SoC: 7 Series FPGA with ARM Cortex A9 866 MHz dual-core processor Analog Devices AD9361 RFIC direct-conversion transceiver Frequency range: 70 MHz - 6 GHz Up to 56 MHz of instantaneous bandwidth 2x2 MIMO transceiver Up to 10 MS/s sample data transfer rate to ARM processor RX, TX filter banks Integrated GPS receiver 9-axis inertial measurement unit RF Network on Chip (RFNoC™) FPGA development framework support

Daughterboard Specifications

E310 MIMO XCVR board

The USRP E310 MIMO XCVR daughterboard features an integrated MIMO capable RF frontend.

Tuning

The RF frontend has individually tunable receive and transmit chains. Both transmit and receive can be used in a MIMO configuration. For the MIMO case, both receive frontends share the RX LO, and both transmit frontends share the TX LO. Each LO is tunable between 50 MHz and 6 GHz.

Gains

All frontends have individual analog gain controls. The receive frontends have 76 dB of available gain; and the transmit frontends have 89.5 dB of available gain. Gain settings are application specific, but it is recommended that users consider using at least half of the available gain to get reasonable dynamic range.

LO lock status

The frontends provide a lo-locked sensor that can be queried through the UHD API.

// assumes 'usrp' is a valid uhd::usrp::multi_usrp::sptr instance
// get status for rx frontend
usrp->get_rx_sensor("lo-locked");
// get status for tx frontend
usrp->get_tx_sensor("lo-locked");

Filter and Antenna Switches

The transmit and receive filter banks uses switches to select between the available filters. These paths are also dependent on the antenna switch settings. Incorrectly setting the switches generally results in attenuated input / output power. Receive filters are band pass (series high & low pass filters), transmit filters are low pass.

Source code related to controlling the filter band and antenna switches resides in e300_impl.c. Specifically, refer to methods e300_impl::_update_bandsel, e300_impl::_update_atrs, e300_impl::_update_gpio, and e300_impl::_update_enables. Generally, these methods set the switches depending on the state of transmit and receive streams.

The following sections provide switch setting tables for antenna and filter selection for frontends A & B receive and transmit paths. For futher details refer to the schematics.

Side A Filter and Antenna Switches

Note: X = don't care, T = If full duplex, set bits according to transmit table, otherwise don't care. Filter range A – B will be selected if A <= freq < B.

Receive

Transmit

Note: Although the transmit filters are low pass, this table describes UHD's tuning range for selecting each filter path. The table also includes the required transmit enable state.

Side B Filter and Antenna Switches

Note: X = don't care, T = If full duplex, set bits according to transmit table, otherwise don't care. Filter range A – B will be selected if A <= freq < B.

Receive

Transmit

Note: Although the transmit filters are low pass, the following table describes UHD's tuning range for selecting each filter path. The table also includes the required transmit enable states.

RF Specifications

RF Performance

• SSB/LO Suppression -35/50 dBc
• Phase Noise 3.5 GHz 1.0 deg RMS
• Phase Noise 6 GHz 1.5 deg RMS
• Power Output >10dBm
• IIP3 (@ typ NF) -20dBm
• Typical Noise Figure <8dB

Input/Output Impedance

• All RF Ports are matched to 50 Ohm with -10dB or better return loss generally. Detailed test is pending.

Hardware Specifications

• Ettus Research recommends to always use the latest stable version of UHD

E310

• Current Hardware Revision: 1
• Minimum version of UHD required: 3.8.0
• Required version on the host computer must match what is running on the E310

E312

• Current Hardware Revision: 1
• Minimum version of UHD required: 3.8.5
• Required version on the host computer must match what is running on the E312

Physical Specifications

Dimensions

• 133 x 68 x 26.4 mm

Environmental Specifications

Operating Temperature Range

• E310 0-40 °C
• E312 0-40 °C

Operating Humidity Range

• 10% to 90% non-condensing

Schematics

E310

E310 Schematics

E310 DB

E310 Architecture

Key Component Datasheets

Request a detailed whitepaper covering features and components from info@ettus.com

Mechanical Information

Weight

• Partial Enclosure 225 g
• Full Enclosure 375 g

Drawings

E310

• File:E310 Dimensional Sketches.pdf
• File:cu e310 motherboard cca.pdf
• File:cu E310 daughtercard cca.pdf
• File:cu usrp-e310.pdf

E312

• File:cu e312 motherboard cca.pdf
• File:cu e312 daughtercard cca.pdf
• File:cu ettus-e312.pdf

FPGA

• Utilization statistics are subject to change between UHD releases. This information is current as of UHD 3.9.4 and was taken directly from Xilinx Vivado 2014.4.

E310/E312

1. Slice Logic
--------------

+----------------------------+-------+-----------+-------+
|          Site Type         |  Used | Available | Util% |
+----------------------------+-------+-----------+-------+
| Slice LUTs                 | 36203 |     53200 | 68.05 |
|   LUT as Logic             | 28108 |     53200 | 52.83 |
|   LUT as Memory            |  8095 |     17400 | 46.52 |
|     LUT as Distributed RAM |   870 |           |       |
|     LUT as Shift Register  |  7225 |           |       |
| Slice Registers            | 36562 |    106400 | 34.36 |
|   Register as Flip Flop    | 36562 |    106400 | 34.36 |
|   Register as Latch        |     0 |    106400 |  0.00 |
| F7 Muxes                   |   376 |     26600 |  1.41 |
| F8 Muxes                   |   125 |     13300 |  0.93 |
+----------------------------+-------+-----------+-------+

3. Memory
---------

+-------------------+------+-----------+-------+
|     Site Type     | Used | Available | Util% |
+-------------------+------+-----------+-------+
| Block RAM Tile    |   97 |       140 | 69.28 |
|   RAMB36/FIFO*    |   90 |       140 | 64.28 |
|     RAMB36E1 only |   90 |           |       |
|   RAMB18          |   14 |       280 |  5.00 |
|     RAMB18E1 only |   14 |           |       |
+-------------------+------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1


4. DSP
------

+----------------+------+-----------+-------+
|    Site Type   | Used | Available | Util% |
+----------------+------+-----------+-------+
| DSPs           |  120 |       220 | 54.54 |
|   DSP48E1 only |  120 |           |       |
+----------------+------+-----------+-------+

Interfaces and Connectivity

• 10/100/1000 BASE-T Ethernet
• Stereo audio out, mono mic in
• Integrated GPS receiver
• Host USB support
• 9-axis IMU

Front Panel

RF A Group TX/RX LED: Indicates that data is streaming on the TX/RX channel on frontend side A RX2 LED: Indicates that data is streaming on the RX2 channel on frontend side A RF B Group TX/RX LED: Indicates that data is streaming on the TX/RX channel on frontend B RX2 LED: Indicates that data is streaming on the RX2 channel on frontend B PWR: Power switch with integrated status LED, for status description see below. SYNC: Input port for external PPS signal GPS: Connection for the GPS antenna AUDIO: Audio input / output The status LED in the power switch indicates the power and charge status. It's behavior is firmware version dependent. Version 1 (original E310) Off: Indicates device is off and not charging Solid Red: Indicates device is charging Solid Green: Indicates device is on Fast Blinking Red: Indicates an error code 1 - Low voltage error 2 - Regulator low voltage error 3 - FPGA power error 4 - DRAM power error 5 - 1.8V rail power error 6 - 3.3V rail power error 7 - Daughterboard / TX power error 9 - Temperature error Version 2 (E312 and upgraded E310) Off: Indicates device is off and not charging Slow Blinking Green: Indicates device is off and charging Fast Blinking Green: Indicates device is on and charging Solid Green: Indicates device is on (and not charging, if E312) Solid Orange: Indicates device is on and discharging Fast Blinking Orange: Indicates device is on, discharging, and charge is below 10% charge Fast Blinking Red: Indicates an error code 1 - Low voltage error 2 - Regulator low voltage error 3 - FPGA power error 4 - DRAM power error 5 - 1.8V rail power error 6 - 3.3V rail power error 7 - Daughterboard / TX power error 8 - Charger error 9 - Charger temperature error 10 - Battery low error 11 - Fuel Gauge temperature error 12 - Global (case) temperature error

Rear Panel