Difference between revisions of "B100"
From Ettus Knowledge Base
(→FPGA) |
|||
| Line 16: | Line 16: | ||
==FPGA== | ==FPGA== | ||
| + | * Utilization statistics are subject to change between UHD releases, current as of UHD 3.9.4 | ||
| + | |||
===B100=== | ===B100=== | ||
<pre> | <pre> | ||
Revision as of 18:18, 2 May 2016
Contents
Key Features
USRP B100
- 16 MHz of RF bandwidth with 8 bit samples
- 8 MHz of RF bandwidth with 16 bit samples
- USB 2.0 high speed connectivity
- Motherboard has one RTX daughterboard slot (1 RX + 1 TX connectors)
- Onboard FPGA processing
- FPGA: Xilinx Spartan 3A-1400 FPGA
- ADCs: 12-bits 64 MS/s
- DACs: 14-bits 128 MS/s
- Ability to lock to external 5 or 10 MHz clock reference
- TCXO Frequency Reference (~2.5ppm)
- Flexible clocking from 10 MHz to 64 MHz
- FPGA code can be changed with Xilinx® ISE® WebPACK™ tools
FPGA
- Utilization statistics are subject to change between UHD releases, current as of UHD 3.9.4
B100
Device utilization summary:
---------------------------
Selected Device : 3s1400aft256-4
Number of Slices: 10238 out of 11264 90%
Number of Slice Flip Flops: 12136 out of 22528 53%
Number of 4 input LUTs: 18184 out of 22528 80%
Number used as logic: 15003
Number used as Shift registers: 2605
Number used as RAMs: 576
Number of IOs: 150
Number of bonded IOBs: 148 out of 161 91%
IOB Flip Flops: 140
Number of BRAMs: 31 out of 32 96%
Number of MULT18X18SIOs: 20 out of 32 62%
Number of GCLKs: 2 out of 24 8%
