B100

End-of-Life (EOL)

Please note that this product is now End-of-Life (EOL), and is no longer available for sale through Ettus Research, and is not recommended for use in new designs or in new projects.

Key Features

USRP B100

• 16 MHz of RF bandwidth with 8 bit samples
• 8 MHz of RF bandwidth with 16 bit samples
• USB 2.0 high speed connectivity
• Motherboard has one RTX daughterboard slot (1 RX + 1 TX connectors)
• Onboard FPGA processing
• FPGA: Xilinx Spartan 3A-1400 FPGA
• ADCs: 12-bits 64 MS/s
• DACs: 14-bits 128 MS/s
• Ability to lock to external 5 or 10 MHz clock reference
• TCXO Frequency Reference (~2.5ppm)
• Flexible clocking from 10 MHz to 64 MHz
• FPGA code can be changed with Xilinx® ISE® WebPACK™ tools

FPGA

• Utilization statistics are subject to change between UHD releases, current as of UHD 3.9.4

B100

Device utilization summary:
---------------------------

Selected Device : 3s1400aft256-4

 Number of Slices:                    10238  out of  11264    90%
 Number of Slice Flip Flops:          12136  out of  22528    53%
 Number of 4 input LUTs:              18184  out of  22528    80%
    Number used as logic:             15003
    Number used as Shift registers:    2605
    Number used as RAMs:                576
 Number of IOs:                         150
 Number of bonded IOBs:                 148  out of    161    91%
    IOB Flip Flops:                     140
 Number of BRAMs:                        31  out of     32    96%
 Number of MULT18X18SIOs:                20  out of     32    62%
 Number of GCLKs:                         2  out of     24     8%

Proper Care and Handling

All Ettus Research products are individually tested before shipment. The USRP B100 is guaranteed to be functional at the time it is received by the customer. Improper use or handling of the USRP B100 can easily cause the device to become non-functional. Listed below are some examples of actions which can prevent damage to the unit:

• Never allow metal objects to touch the circuit board while powered.
• Always properly terminate the transmit port with an antenna or 50Ω load.
• Always handle the board with proper anti-static methods.
• Never allow the board to directly or indirectly come into contact with any voltage spikes.
• Never allow any water, or condensing moisture, to come into contact with the boards.
• Always use caution with FPGA, firmware, or software modifications.

	Never apply more than -15 dBm of power into any RF input.
	Always use at least 30dB attenuation if operating in loopback configuration